公开(公告)号：US11894359B2

公开(公告)日：2024-02-06

申请号：US17574485

申请日：2022-01-12

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark T. Bohr ,  Rajesh Kumar ,  Robert L. Sankman ,  Ravindranath V. Mahajan ,  Wesley D. McCullough

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L25/00 ,  H01L23/538 ,  H01L23/522 ,  H01L25/16 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L23/49816 ,  H01L2924/1432

Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

公开(公告)号：US11824041B2

公开(公告)日：2023-11-21

申请号：US17226967

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20210335791A1

公开(公告)日：2021-10-28

申请号：US17368329

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/786 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20210134802A1

公开(公告)日：2021-05-06

申请号：US16669599

申请日：2019-10-31

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Tahir Ghani ,  Doug Ingerly ,  Rajesh Kumar

IPC: H01L27/108

Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.

公开(公告)号：US09939882B2

公开(公告)日：2018-04-10

申请号：US13954977

申请日：2013-07-31

Applicant: Intel Corporation

Inventor： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC: G06F9/00 ,  G06F15/177 ,  G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.

公开(公告)号：US11984430B2

公开(公告)日：2024-05-14

申请号：US18128958

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US11830829B2

公开(公告)日：2023-11-28

申请号：US17836117

申请日：2022-06-09

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Doug Ingerly ,  Rajesh Kumar ,  Harish Krishnamurthy ,  Nachiket Venkappayya Desai

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06558 ,  H01L2225/06582 ,  H01L2924/19042

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

公开(公告)号：US11373987B2

公开(公告)日：2022-06-28

申请号：US16646460

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark Bohr ,  Glenn J. Hinton ,  Rajesh Kumar

IPC: H01L21/00 ,  H01L25/18 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

公开(公告)号：US11257822B2

公开(公告)日：2022-02-22

申请号：US16691163

申请日：2019-11-21

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Kinyip Phoa ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Uygar E. Avci ,  Rajesh Kumar

IPC: H01L27/108 ,  H01L29/78 ,  H01L49/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.

公开(公告)号：US09829965B2

公开(公告)日：2017-11-28

申请号：US14498014

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Herbert Hum ,  Eric Sprangle ,  Douglas Carmean ,  Rajesh Kumar

IPC: G06F1/24 ,  G06F9/00 ,  G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques are disclosed to control power and processing among a plurality of asymmetric cores. In one embodiment, a multi-core processor includes first and second processing cores, each including an arithmetic logic unit and an instruction decoder, wherein the first processing core is capable of operating at a higher processing throughput than the second processing core, wherein the first and second processing cores have different instruction sets, wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core, wherein instructions to run on the second processing core are translated to the instruction set of the second processing core by a software binary translation shell, and wherein the first and second processing cores are to concurrently execute instructions according to their own instruction sets.