公开(公告)号：US11854931B2

公开(公告)日：2023-12-26

申请号：US16721807

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chia-Pin Chiu ,  Peng Li ,  Shankar Devasenathipathy

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/5386 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2225/06589

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.

公开(公告)号：US11581671B2

公开(公告)日：2023-02-14

申请号：US16361537

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Steven A. Klein ,  Chia-Pin Chiu ,  Shankar Devasenathipathy

IPC: H01R13/62 ,  H01R12/70 ,  H01R13/50 ,  H01R13/24 ,  H01R12/71

Abstract: An integrated circuit (IC) socket comprising a housing with a land side, an opposing die side, and sidewalls around a perimeter of the housing. The housing comprises a first dielectric. A plurality of socket pins extends from the land side of the housing through socket pin holes in the housing over the die side of the housing. A second dielectric is within the interstitial regions between the socket pins and sidewalls of the socket pin holes. A frame structure extends around at least a portion of the perimeter of the housing, and a mesh structure is embedded within the first dielectric. The mesh structure has plurality of mesh filaments extending between the plurality of socket pin holes and coupled to the frame structure.

公开(公告)号：US11444003B2

公开(公告)日：2022-09-13

申请号：US16144584

申请日：2018-09-27

Applicant: INTEL CORPORATION

Inventor： Zhimin Wan ,  Chia-Pin Chiu ,  Chandra Mohan Jha ,  Weihua Tang ,  Shankar Devasenathipathy

IPC: H01L23/473 ,  H01L25/18 ,  H01L23/467 ,  H01L23/367 ,  H01L23/373

Abstract: An integrated heat spreader includes channel structures assembled in a frame. Each channel structure is independent of the other, and can be used to dissipate heat from integrated circuitry at a specific location within a package, and without allowing heat from that particular location to propagate to integrated circuitry at other locations within the package. Each channel structure can be implemented with metal having a high thermal conductivity (e.g., copper). The channel structures can be used in conjunction with liquid-based cooling or air-based cooling. The frame can be implemented with low thermal conductivity molding compound or plastic so the heat transfer from one channel structure to another is inhibited. The channel structures can have different configurations (e.g., straight, pillars, and/or pin fins) to provide different rates of flow, mixing, and/or cooling. The flow direction of air or liquid for the channel structures can be the same (parallel) or different (counter).

公开(公告)号：US20210375719A1

公开(公告)日：2021-12-02

申请号：US17399882

申请日：2021-08-11

Applicant: Intel Corporation

Inventor： Feras Eid ,  Shrenik Kothari ,  Chandra M. Jha ,  Johanna M. Swan ,  Michael J. Baker ,  Shawna M. Liff ,  Thomas L. Sounart ,  Betsegaw K. Gebrehiwot ,  Shankar Devasenathipathy ,  Taylor Gaines ,  Digvijay Ashokkumar Raorane

IPC: H01L23/433 ,  H01L23/29 ,  H01L21/56 ,  H01L25/00 ,  H01L25/18 ,  H01L23/42 ,  H01L23/367 ,  H01L23/04 ,  H01L25/065 ,  H01L25/16 ,  H01L23/16

Abstract: A semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.

公开(公告)号：US20230290706A1

公开(公告)日：2023-09-14

申请号：US17693003

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Gaurav Patankar ,  Shankar Devasenathipathy ,  Krishna Vasanth Valavala

IPC: H01L23/427 ,  H01L23/367 ,  H01L23/473

CPC classification number: H01L23/427 ,  H01L23/3672 ,  H01L23/473

Abstract: A surplus liquid reservoir attached to a vapor chamber integrated heat spreader (IHS) and placed near a heat source on a heterogenous die. The vapor chamber integrated heat spreader (IHS) includes a main heat transfer portion that encloses a vapor channel, a first wick material, and a first working fluid. The surplus liquid reservoir is provided by a reservoir leg mechanically coupled, on a first side, to the main heat transfer portion, the reservoir leg has a reservoir portion with a second working fluid and second wick material that is in contact with the first wick material. The surplus liquid reservoir can either support a PL2 that is higher than a given vapor chamber Qmax for a significantly long time or increase the PL2 value to a significantly higher value.

公开(公告)号：US11646244B2

公开(公告)日：2023-05-09

申请号：US16454343

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Steven A. Klein ,  Zhimin Wan ,  Chia-Pin Chiu ,  Shankar Devasenathipathy

IPC: H01L23/40 ,  H01R12/71 ,  H01R13/73 ,  H01L23/427

CPC classification number: H01L23/4006 ,  H01L23/427 ,  H01R12/716 ,  H01R13/73 ,  H01L2023/4062 ,  H01L2023/4087

Abstract: A microprocessor mounting apparatus comprising a microprocessor socket on a printed circuit board (PCB) and a bolster plate surrounding a perimeter of the microprocessor socket. The bolster plate has a first surface adjacent to the PCB, and a second surface opposite the first surface. A heat dissipation device is on the second surface of the bolster plate. The heat dissipation interface is thermally coupled to the microprocessor socket.

公开(公告)号：US11322456B2

公开(公告)日：2022-05-03

申请号：US16611830

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Venkata Suresh R. Guthikonda ,  Shankar Devasenathipathy ,  Chandra M. Jha ,  Je-Young Chang ,  Kyle Yazzie ,  Prasanna Raghavan ,  Pramod Malatkar

IPC: H05K1/18 ,  H01L23/00 ,  H01L21/50 ,  H01L23/544 ,  H01L25/065 ,  H05K1/02

Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.

公开(公告)号：US20200312741A1

公开(公告)日：2020-10-01

申请号：US16362961

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Krishna Vasanth Valavala ,  Chandra Mohan Jha ,  Shankar Devasenathipathy

IPC: H01L23/38 ,  H01L23/373 ,  H01L35/32

Abstract: An IC package comprising a substrate comprising a dielectric, an IC device coupled to the substrate; and a thermoelectric cooling (TEC) device adjacent to the IC device and coupled to the substrate. A thermal trace extends laterally on or within the dielectric between the TEC device to the IC device, and the thermal trace is coupled to the TEC device and the IC device.

公开(公告)号：US10600699B2

公开(公告)日：2020-03-24

申请号：US15685772

申请日：2017-08-24

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Shankar Devasenathipathy ,  Joseph B. Petrini

IPC: H01L21/66 ,  G01K7/22 ,  H01L23/498 ,  G01K1/02 ,  G01K1/14 ,  H01L23/427

Abstract: Embodiments of the present disclosure provide techniques and configurations for inspection of a package assembly with a thermal solution, in accordance with some embodiments. In embodiments, an apparatus for inspection of a package assembly with a thermal solution may include a first fixture to house the package assembly on the apparatus, and a second fixture to house at least a portion of a thermal solution that is to be disposed on top of the package assembly. The apparatus may further include a load actuator, to apply a load to a die of the package assembly, via the thermal solution, and a plurality of sensors disposed around the thermal solution and the package assembly, to perform in situ thermal and/or mechanical measurements associated with the application of the load to the die of the package assembly. Other embodiments may be described and/or claimed.

公开(公告)号：US09943931B2

公开(公告)日：2018-04-17

申请号：US15221102

申请日：2016-07-27

Applicant: Intel Corporation

Inventor： Zhihua Li ,  Hemanth K. Dhavaleswarapu ,  Joseph B. Petrini ,  Shankar Devasenathipathy ,  Steven B. Roach ,  Ioan Sauciuc ,  Pranav K. Desai ,  George S. Kostiew ,  Sanjoy K. Saha

IPC: B23K37/00 ,  B23K3/08 ,  H01L23/00 ,  H05K3/34 ,  B23K20/02 ,  F25B21/02

CPC classification number: B23K37/003 ,  B23K3/085 ,  B23K20/023 ,  F25B21/02 ,  F25B2321/0251 ,  H01L24/13 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/291 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75502 ,  H01L2224/81203 ,  H01L2224/83203 ,  H05K3/34 ,  H01L2924/014

Abstract: Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.