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    RECESSED THIN-CHANNEL THIN-FILM TRANSISTOR
    12.
    发明申请
    RECESSED THIN-CHANNEL THIN-FILM TRANSISTOR 有权

    公开(公告)号：US20220029025A1

    公开(公告)日：2022-01-27

    申请号：US17496690

    申请日：2021-10-07

    Applicant: Intel Corporation

    Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Yih WANG

    IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

    Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

    COMPUTE NEAR MEMORY WITH BACKEND MEMORY
    14.
    发明申请
    COMPUTE NEAR MEMORY WITH BACKEND MEMORY 审中-公开

    公开(公告)号：US20200279850A1

    公开(公告)日：2020-09-03

    申请号：US16827542

    申请日：2020-03-23

    Applicant: Intel Corporation

    Inventor： Abhishek SHARMA ,  Noriyuki SATO ,  Sarah ATANASOV ,  Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Hui Jae YOO ,  Van H. LE

    IPC: H01L27/108 ,  H01L27/12 ,  G11C11/4096

    Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

    SPACER-PATTERNED INVERTERS BASED ON THIN-FILM TRANSISTORS
    15.
    发明申请
    SPACER-PATTERNED INVERTERS BASED ON THIN-FILM TRANSISTORS 审中-公开

    公开(公告)号：US20200211911A1

    公开(公告)日：2020-07-02

    申请号：US16637932

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Gilbert DEWEY ,  Willy RACHMADY

    IPC: H01L21/84 ,  H01L27/12

    Abstract: A semiconductor device may include a first gate electrode and a second gate electrode. A first channel area and a second channel area may be above the first gate electrode, where the first channel area may include a first type channel material, and the second channel area may include a second type channel material. A third channel area and a fourth channel area may be above the second gate electrode, where the third channel area may include the first type channel material, and the fourth channel area may include the second type channel material. The third channel area may be separated from the first channel area by a spacer. An inverter may include the first gate electrode, the first channel area, and the second channel area, while another inverter may include the second gate electrode, the third channel area, and the fourth channel area. Other embodiments may be described/claimed.

    A VERTICAL 1T-1C DRAM ARRAY
    16.
    发明申请
    A VERTICAL 1T-1C DRAM ARRAY 审中-公开

    公开(公告)号：US20190355726A1

    公开(公告)日：2019-11-21

    申请号：US16480627

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Ravi PILLARISETTY ,  Van H. LE ,  Gilbert DEWEY ,  Abhishek A. SHARMA

    IPC: H01L27/108

    Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

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