公开(公告)号：US20170286221A1

公开(公告)日：2017-10-05

申请号：US15086050

申请日：2016-03-30

Applicant: INTEL CORPORATION

Inventor： Tal AZOGUI ,  Vered BAR BRACHA ,  Vallabhajosyula S. SOMAYAZULU ,  Wei WU

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F3/067 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

Abstract: Provided are a method and apparatus for an error tolerance aware data retention scheme in a storage device for multi-scale error tolerant data. A mapping of retention priorities to sectors of the storage units maps higher retention priorities to sectors having a higher retention capability. A data stream and retention metadata for the data stream indicate retention priorities for segments of the data stream. Segments of the data stream having less error tolerance are mapped to higher retention priorities than segments of the data stream having greater error tolerance. The mapping of retention priorities is used to determine a sector having a retention priority matching a retention priority of a segment of the data stream indicated in the retention metadata. The segment of the data stream is stored in the determined sector.

公开(公告)号：US20170178708A1

公开(公告)日：2017-06-22

申请号：US15371122

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  Wei WU ,  Shih-Lien LU ,  James W. TSCHANZ ,  Georgios PANAGOPOULOS ,  Helia NAEIMI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

公开(公告)号：US20170126249A1

公开(公告)日：2017-05-04

申请号：US14929163

申请日：2015-10-30

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  Shih-lien L. LU ,  James W. TSCHANZ

IPC: H03M13/05 ,  H03M13/00

CPC classification number: H03M13/05 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/353 ,  H03M13/611 ,  H03M13/6502 ,  H03M13/6516

Abstract: In one embodiment, temperature dependent, multiple mode error correction in accordance with one aspect of this disclosure, is employed for a memory circuit containing arrays of memory cells. In one embodiment, a temperature sensor coupled to an array is configured to provide an output signal which is a function of the temperature of the array of memory cells. Multiple mode error correction code (ECC) logic having an input coupled to an output of the temperature sensor, is configured to encode write data and decode read data for the array of memory cells in an error correction code in one of a plurality of error correction modes as a function of the temperature of the array of memory cells. Other aspects are described herein.

公开(公告)号：US20240061741A1

公开(公告)日：2024-02-22

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Hsing-Min CHEN ,  Wei P. CHEN ,  Wei WU ,  Jing LING ,  Kuljit S. BAINS ,  Kjersten E. CRISS ,  Deep K. BUCH ,  Theodros YIGZAW ,  John G. HOLM ,  Andrew M. RUDOFF ,  Vaibhav SINGH ,  Sreenivas MANDAVA

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US20210019225A1

公开(公告)日：2021-01-21

申请号：US17031772

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Byoungchan OH ,  Wei WU

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/29

Abstract: Examples include techniques to improve implement an error correction codeword (ECC) scheme to protect data stored to a memory from both hard and random bit errors using a hybrid ECC scheme that includes generation of first and second codewords to protect the data.

公开(公告)号：US20170177519A1

公开(公告)日：2017-06-22

申请号：US14975293

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Shigeki TOMISHIMA ,  Shih-Lien L. LU

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/1668 ,  G06F13/4027

Abstract: Provided are a memory device and a memory bank comprising a split local data bus, and a segmented global data bus coupled to local data bus. Provided also is a method comprising, receiving a signal from a split local data bus, and transmitting the signal to a segmented global data bus coupled to local data bus. Provided also is a computational device that includes the memory device and the memory bank, and optionally one or more of a display, a network interface, and a battery.

公开(公告)号：US20170153933A1

公开(公告)日：2017-06-01

申请号：US15374922

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA ,  Charles AUGUSTINE ,  Wei WU ,  Shih Lien L. LU

IPC: G06F11/07 ,  G11C11/16 ,  G06F3/06 ,  H03M13/15 ,  H03M13/37 ,  G11C13/00 ,  G06F11/10

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C29/42 ,  G11C29/52 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82 ,  H03M13/1575 ,  H03M13/373 ,  H03M13/6502

Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.

公开(公告)号：US20240020197A1

公开(公告)日：2024-01-18

申请号：US18372525

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Wei WU ,  Hechen WANG

IPC: G06F11/10 ,  G06F11/07 ,  G06F17/16

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F17/16

Abstract: Circuitry for a compute-in-memory (CiM) circuit or structure arranged to detect bit errors in a group of memory cells based on a summation of binary 1's included in at least one weight matrix stored to the group of memory cells, a parity value stored to another group of memory cells and a comparison of the summation or the parity value to an expected value.

公开(公告)号：US20240013850A1

公开(公告)日：2024-01-11

申请号：US18372482

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Wei WU ,  Hechen WANG

IPC: G11C29/52 ,  G11C7/18 ,  G06F7/492

CPC classification number: G11C29/52 ,  G11C7/18 ,  G06F7/4925

Abstract: A compute-in-memory (CiM) circuit or structure arranged to detect errors. Examples include detecting errors associated with weight bits stored to computational nodes included in a CiM circuit or structure based on use of complimented bit values. Examples also include detecting errors in the CiM circuit or structure based on using at least some computational nodes included in an array of computational nodes to monitor for the errors during generation of computation results by other computational nodes included in the array.

公开(公告)号：US20220107867A1

公开(公告)日：2022-04-07

申请号：US17553623

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Wei WU ,  Carlos TOKUNAGA ,  Gregory K. CHEN

IPC: G06F11/10

Abstract: A near memory compute system includes multiple computation nodes, such as nodes for parallel distributed processing. The nodes include a memory device to store data and compute hardware to perform a computation on the data. Error correction code (ECC) logic performs ECC on the data prior to computation on the data by the compute hardware. The node also includes residue check logic to perform a residue check on a result of the computation.