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公开(公告)号：US09059051B2
公开(公告)日：2015-06-16
申请号：US13889374
申请日：2013-05-08
Applicant: International Business Machines Corporation
Inventor： Hanyi Ding , J. Edwin Hostetter, Jr. , Ping-Chuan Wang , Kimball M. Watson
IPC: H01L21/66
CPC classification number: H01L22/26 , H01L21/304 , H01L22/14 , H01L22/34
Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.
Abstract translation: 公开了一种通过硅通孔（TSV）电容测试结构和基于电容确定TSV深度的方法。 TSV电容测试结构由均匀间隔的多个TSV条形成。 第一组电杆电连接以形成第一电容器节点，并且第二组电杆电连接以形成第二电容器节点。 测量电容，并在背面变薄之前计算TSV深度。 然后计算的TSV深度可以被馈送到下游研磨和/或抛光工具以控制背面变薄处理，使得半导体晶片变薄使得背面与TSV齐平。
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12.发明授权Micro-electro-mechanical system (MEMS) capacitive ohmic switch and design structures 有权微机电系统（MEMS）电容欧姆开关和设计结构公开(公告)号：US09006797B2
公开(公告)日：2015-04-14
申请号：US14041983
申请日：2013-09-30
Applicant: International Business Machines Corporation
Inventor： Hanyi Ding , Qizhi Liu , Anthony K. Stamper
CPC classification number: H01H1/0036 , B81B7/0006 , B81B2201/016 , G06F17/5063 , G06F17/5068 , H01P1/127
Abstract: A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method includes forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method includes forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method includes forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method includes forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.
Abstract translation: 提供了微机电系统（MEMS），形成MEMS和设计结构的方法。 该方法包括在衬底上形成包括信号电极和一对电极的共面波导（CPW）。 该方法包括在CPW上形成第一牺牲材料，以及在第一牺牲材料上方和CPW上方的布线层。 该方法包括在布线层上形成第二牺牲材料层，以及围绕第一牺牲材料和第二牺牲材料形成绝缘体材料。 所述方法包括在所述绝缘体材料中形成至少一个通气孔以暴露所述第二牺牲材料的部分，以及通过所述通气孔去除所述第一和第二牺牲材料以形成围绕所述布线层的空腔结构，并且暴露所述信号线和 一对电极在布线层下方。 通气孔用密封材料密封。
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公开(公告)号：US08947160B2
公开(公告)日：2015-02-03
申请号：US14067122
申请日：2013-10-30
Applicant: International Business Machines Corporation
Inventor： Hanyi Ding , Kwan Him Lam
Abstract: A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler.
Abstract translation: Lange耦合器，其具有在第一电平上的第一多个线，而在第二电平上具有第二多个线。 在第一级上的至少一条线通过在第一和第二条线上行进的电磁波交叉耦合到第二电平上的相应线。 第一和第二多个线可以由金属制成，并且第一电平可以高于第二电平。 可以提供衬底，其中蚀刻第一和第二多条线以便限定片上朗格耦合器。
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公开(公告)号：US08859300B2
公开(公告)日：2014-10-14
申请号：US13738367
申请日：2013-01-10
Applicant: International Business Machines Corporation
Inventor： Hanyi Ding , Wayne H. Woods, Jr.
IPC: H01L23/00 , H01L49/02 , G06F17/50 , H01L23/522 , H01L27/08
CPC classification number: H01L28/10 , G06F17/5068 , G06F17/5077 , H01L21/31053 , H01L21/76808 , H01L21/76826 , H01L23/5223 , H01L23/5227 , H01L27/08 , H01L29/432 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.
Abstract translation: 包括信号传输金属线和电容接地感应信号耦合金属线的一组金属线结构被嵌入在电介质材料层中。 电容器串联连接在电容接地的感应信号耦合金属线路和可能在输入侧或输出侧的局部电接地之间。 金属线结构和电容集合提供了一个频率相关的电感。 频率依赖电感器的Q因子具有多个峰值，使得能够在多个频率下操作频率相关的电感器。 可以在频率相关电感器中提供多个电容耦合的感应信号耦合金属线路，每个电路通过电容器连接到本地电接地。 通过选择电容器的不同电容值，可以在不同信号频率的频率相关电感器中获得Q因子的多个值。
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公开(公告)号：US08806415B1
公开(公告)日：2014-08-12
申请号：US13768112
申请日：2013-02-15
Applicant: International Business Machines Corporation
Inventor： Hanyi Ding , Kai D. Feng , Hailing Wang
IPC: G06F17/50
CPC classification number: G06F17/5036 , G06F2217/40
Abstract: A method of modeling an integrated circuit chip includes generating a model of a bond pad using a design tool running on a computer device. The method also includes connecting a first inductor, a first resistor, and a first set of parallel-resistor-inductor elements in series between a first node and a second node in the model. The method further includes connecting a second inductor, a second resistor, and a second set of parallel-resistor-inductor elements in series between the second node and a third node in the model. The first node corresponds to a first signal port of the bond pad. The second node corresponds to a second signal port of the bond pad.
Abstract translation: 对集成电路芯片进行建模的方法包括使用在计算机设备上运行的设计工具来生成焊盘的模型。 该方法还包括在模型中的第一节点和第二节点之间串联连接第一电感器，第一电阻器和第一组并联电阻器 - 电感器元件。 该方法还包括在模型中的第二节点和第三节点之间串联连接第二电感器，第二电阻器和第二组并联电阻器 - 电感器元件。 第一个节点对应于接合焊盘的第一个信号端口。 第二节点对应于接合焊盘的第二信号端口。
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Patent Agency Ranking
公开(公告)号：US20130161785A1
公开(公告)日：2013-06-27
申请号：US13771668
申请日：2013-02-20
Applicant: International Business Machines Corporation
Inventor： Hanyi Ding , Wayne H. Woods
IPC: H01L49/02
CPC classification number: H01L28/10 , G06F17/5068 , G06F17/5077 , H01L21/31053 , H01L21/76808 , H01L21/76826 , H01L23/5223 , H01L23/5227 , H01L27/08 , H01L29/432 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.
Abstract translation: 包括信号传输金属线和电容接地感应信号耦合金属线的一组金属线结构被嵌入在电介质材料层中。 电容器串联连接在电容接地的感应信号耦合金属线路和可能在输入侧或输出侧的局部电接地之间。 金属线结构和电容集合提供了一个频率相关的电感。 频率依赖电感器的Q因子具有多个峰值，使得能够在多个频率下操作频率相关的电感器。 可以在频率相关电感器中提供多个电容耦合的感应信号耦合金属线路，每个电路通过电容器连接到本地电接地。 通过选择电容器的不同电容值，可以在不同信号频率的频率相关电感器中获得Q因子的多个值。
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公开(公告)号：US09728838B2
公开(公告)日：2017-08-08
申请号：US14687002
申请日：2015-04-15
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Hanyi Ding , Mark D. Jaffe , Alvin J. Joseph , Anthony K. Stamper
IPC: H01L21/76 , H01L23/52 , H01Q1/22 , H01L21/762 , H01Q9/16
CPC classification number: H01Q1/2283 , H01L21/76224 , H01L23/5227 , H01Q9/16
Abstract: Approaches for an on-chip antenna are provided. A method includes forming an antenna in an insulator layer at a front side of a substrate. The method also includes forming a trench in the substrate underneath the antenna. The method further includes forming a fill material in the trench. The substrate is composed of a material having a first dielectric constant. The fill material has a second dielectric constant that is less than the first dielectric constant.
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公开(公告)号：US09461612B2
公开(公告)日：2016-10-04
申请号：US14285145
申请日：2014-05-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Hanyi Ding , Alberto Valdes Garcia , Wayne H. Woods, Jr.
Abstract: A reconfigurable rat race coupler and methods of designing and reconfiguring the rat race coupler are disclosed. The reconfigurable rat race coupler, includes a plurality of transmission lines. The plurality of transmission lines include: a first transmission line and a second transmission line each of which comprise a phase shifter; and a third transmission line and a fourth transmission line each of which comprise phase shifters. A signal input on port 1 is provided between the phase shifters on the third transmission line, which is split between ports 2 and 3, with port 4 being isolated and port 2 being between the phase shifters on the fourth transmission line.
Abstract translation: 公开了一种可重构的大鼠赛跑耦合器以及设计和重新配置大鼠赛跑耦合器的方法。 可重构的大鼠赛跑耦合器包括多条传输线。 多个传输线包括：第一传输线和第二传输线，每个传输线包括移相器; 以及包括移相器的第三传输线和第四传输线。 端口1上的信号输入设置在端口2和3之间的第三传输线上的移相器之间，端口4被隔离，端口2位于第四传输线上的移相器之间。
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公开(公告)号：US09408304B2
公开(公告)日：2016-08-02
申请号：US14161228
申请日：2014-01-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Dana H. Brown , Hanyi Ding , Yan Ding , John S. Ferrario
CPC classification number: H05K1/115 , H05K1/0222 , H05K1/0251 , H05K1/0298 , H05K1/09 , H05K1/11 , H05K3/4697 , H05K2201/10189 , Y10T29/49004
Abstract: A broadband through printed circuit board (PCB) for millimeter wave application and methods of manufacture are disclosed. The structure includes a multiple layered body and an opening in the multiple layered body. The structure further includes at least one signal via extending through the opening. The structure further includes ground vias extending through the opening and on opposing sides of the at least one signal via. The structure further includes a ground plate above and below the opening and electrically connected to the ground vias at respective ends. The structure further includes a microstrip signal via above and below the opening and electrically connected to the at least one signal via.
Abstract translation: 公开了一种用于毫米波应用的印刷电路板（PCB）和制造方法的宽带。 该结构包括多层体和多层体中的开口。 该结构还包括延伸穿过开口的至少一个信号。 所述结构还包括延伸穿过所述开口和所述至少一个信号通孔的相对侧的接地通孔。 该结构还包括在开口上方和下方的接地板，并在相应端部电连接到接地孔。 该结构还包括通过开口上方和下方并且电连接到至少一个信号通孔的微带信号。
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20.发明授权Millimeter wave wafer level chip scale packaging (WLCSP) device and related method 有权毫米波晶片级芯片级封装（WLCSP）器件及相关方法公开(公告)号：US09159692B2
公开(公告)日：2015-10-13
申请号：US14519590
申请日：2014-10-21
Applicant: International Business Machines Corporation
Inventor： Hanyi Ding , Richard S. Graf , Gary R. Hill , Wayne H. Woods, Jr.
IPC: H01L23/492 , H01L23/00 , H01L23/498 , H01L23/522 , H01L23/66 , H01L21/66 , H01L23/31
CPC classification number: H01L24/17 , H01L22/12 , H01L22/14 , H01L23/3114 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L23/5225 , H01L23/66 , H01L24/09 , H01L2224/0401 , H01L2224/16055 , H01L2224/16225 , H01L2224/16227 , H01L2224/1713 , H01L2924/0002 , H01L2924/1532 , H01L2924/2076 , H01L2924/00
Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.
Abstract translation: 各种实施例包括晶片级芯片级封装（WLCSP）结构和调谐这种结构的方法。 在一些实施例中，WLCSP结构包括：印刷电路板（PCB）迹线连接，其包括与PCB接地平面连接的至少一个PCB接地连接; 一组接地焊球，每个接触印刷电路板跟踪连接; 与所述一组接地焊球中的所述接地焊球接触的一组芯片焊盘; 连接该组芯片焊盘的芯片接地平面; 以及插入在所述一组接地焊球中的两个之间的信号互连，所述信号互连包括：与所述PCB接地平面电隔离的信号迹线连接; 信号球接触信号PCB跟踪连接; 接触信号球的芯片焊盘和与芯片焊盘接触的芯片上的信号迹线连接。
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