Abstract:
Tamper-respondent assemblies and methods of fabrication are provided which include an electronic enclosure and a tamper-respondent electronic circuit structure. The electronic enclosure encloses, at least in part, at least one electronic component to be protected, and includes an inner main surface, and an inner sidewall surface which has at least one inner-sidewall corner. The tamper-respondent electronic circuit structure includes a tamper-respondent sensor covering, at least in part, the inner sidewall surface of the electronic enclosure. The tamper-respondent sensor includes a flexible layer(s) with tamper-detect circuit lines and multiple slots provided therein. The multiple slots facilitate disposing the tamper-respondent sensor to cover the at least one inner-sidewall corner of the inner sidewall surface by allowing for one or more regions of overlap of the flexible layer(s) of the tamper-respondent sensor at the at least one inner-sidewall corner of the electronic enclosure.
Abstract:
A clamping apparatus and method for maintaining a workpiece flatness during processing includes a base having a planar surface for receiving a first workpiece. Two sets of opposing clamping mechanisms are mounted to the base and include a clamp head at a distal end of a rod extending from a housing in removable overlapping relation to the first workpiece. Each set of the clamp heads are in opposing spaced relationship to each other defining a second workpiece area, and the clamp heads are configured to mate with a top surface of the first workpiece. A biasing member is coupled to each of the housings and apply a downward vertical force to the housings, rods, and the clamp heads for applying a downward vertical pressure to the first workpiece. The first workpiece is thereby discouraged from thermally expanding in a vertical direction and is thermally expandable horizontally along the planar surface.
Abstract:
A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.
Abstract:
A fluxless bonding process is provided. An array of micro solder bumps of a first semiconductor structure is aligned to an array of bonding pads of a second semiconductor structure under an applied bonding force. An environment is provided to prevent oxides from forming on the solder bump structures and bonding pads during the bonding process. A scrubbing process is performed at a given scrubbing frequency and amplitude to scrub the micro solder bumps against the bonding pads in a direction perpendicular to the bonding. Heat is applied to at least the first semiconductor structure to melt and bond the micro solder bumps to the bonding pads. The first semiconductor structure is cooled down to solidify the molten solder. Coplanarity is maintained between the bonding surfaces of the semiconductor structures within a given tolerance during the scrubbing and cooling steps until solidification of the micro solder bumps.
Abstract:
A clamping apparatus and method for maintaining a workpiece flatness during processing includes a base having a planar surface for receiving a first workpiece. Two sets of opposing clamping mechanisms are mounted to the base and include a clamp head at a distal end of a rod extending from a housing in removable overlapping relation to the first workpiece. Each set of the clamp heads are in opposing spaced relationship to each other defining a second workpiece area, and the clamp heads are configured to mate with a top surface of the first workpiece. A biasing member is coupled to each of the housings and apply a downward vertical force to the housings, rods, and the clamp heads for applying a downward vertical pressure to the first workpiece. The first workpiece is thereby discouraged from thermally expanding in a vertical direction and is thermally expandable horizontally along the planar surface.
Abstract:
An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.
Abstract:
Methods for preventing warpage of a laminate may include placing the laminate on a back plate and applying a magnetic force to the laminate to hold the laminate flat against the back plate. In some embodiments, the magnetic force may be applied by placing a first magnet above the laminate so that an attractive force generated between the first magnet and a ferromagnetic region of the back plate pulls the first magnet against the laminate, thereby holding the laminate flat against the back plate. In other embodiments, the magnetic force may be applied by placing a first magnet above the laminate and placing a second magnet above the first magnet so that a repulsive force generated between the first magnet and the magnet pushes the first magnet against the laminate, thereby holding the laminate flat against the back plate.
Abstract:
An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.
Abstract:
A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.
Abstract:
An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.