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    Replacement gate with reduced gate leakage current
    12.
    发明授权
    Replacement gate with reduced gate leakage current 有权
    栅极泄漏电流降低的替代栅极

    公开(公告)号：US08809176B2

    公开(公告)日：2014-08-19

    申请号：US13842217

    申请日：2013-03-15

    申请人： International Business Machines Corporation

    发明人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

    摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

    摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

    OXYGEN SCAVENGING SPACER FOR A GATE ELECTRODE
    13.
    发明申请
    OXYGEN SCAVENGING SPACER FOR A GATE ELECTRODE 有权
    用于门电极的氧气隔离器

    公开(公告)号：US20140065783A1

    公开(公告)日：2014-03-06

    申请号：US14073159

    申请日：2013-11-06

    申请人： International Business Machines Corporation

    发明人： Michael P. Chudzik ,  Deleep R. Nair ,  Vijay Narayanan ,  Carl J. Radens ,  Jay M. Shah

    IPC分类号： H01L29/66 ,  H01L21/283 ,  H01L21/28

    CPC分类号： H01L29/66575 ,  H01L21/28017 ,  H01L21/283 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78

    摘要： At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.

    摘要翻译： 包括清除材料和电介质材料的至少一层沉积在栅叠层上，随后进行各向异性蚀刻以形成含氧清除材料的栅间隔物。 含氧清除材料的栅极间隔物可以是包含清除纳米颗粒的栅极间隔物或含有扫气岛的栅极间隔物。 清除材料以防止栅极电极和栅极电介质下方的半导体材料之间的电短路的方式分布在含氧清除材料的栅极间隔物内。 清扫材料主动地清除从可以形成在含氧清除材料的栅极间隔物周围形成的介电栅极隔离物的上方或外部扩散到栅极电介质的氧。

    NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE
    15.
    发明申请
    NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE 有权
    使用高K门电介质和金属门的非易失性存储器结构

    公开(公告)号：US20140057426A1

    公开(公告)日：2014-02-27

    申请号：US14066119

    申请日：2013-10-29

    申请人： International Business Machines Corporation

    发明人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

    IPC分类号： H01L21/28 ,  H01L21/02

    CPC分类号： H01L21/28273 ,  H01L21/0228 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/11546 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7881

    摘要： A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

    摘要翻译： 在半导体衬底上同时形成用于场效应晶体管（FET）的高介电常数（高k）栅极电介质和非易失性随机存取存储器（NVRAM）器件的高k隧道电介质。 随后沉积至少一个导电材料层，控制栅极电介质层和一次性材料层的堆叠并且被光刻图案化。 沉积并图案化平坦化介电层，并且去除一次性材料部分。 控制栅极电介质层的剩余部分保留在NVRAM器件区域中，但在FET区域中被去除。 导电材料沉积在栅极腔中以为NVRAM器件提供控制栅极和用于FET的栅极部分。 或者，控制栅介质层可以用NVRAM器件区域中的高k控制栅极电介质代替。

    REPLACEMENT METAL GATE STRUCTURES FOR EFFECTIVE WORK FUNCTION CONTROL
    16.
    发明申请
    REPLACEMENT METAL GATE STRUCTURES FOR EFFECTIVE WORK FUNCTION CONTROL 有权
    更换用于有效工作功能控制的金属门结构

    公开(公告)号：US20130175635A1

    公开(公告)日：2013-07-11

    申请号：US13780003

    申请日：2013-02-28

    申请人： International Business Machines Corporation

    发明人： Unoh Kwon ,  Michael P. Chudzik ,  Ravikumar Ramachandran

    IPC分类号： H01L27/092

    CPC分类号： H01L27/0922 ,  H01L21/823842

    摘要： A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures.

    摘要翻译： 在替换金属栅极方案中沉积阻挡金属层和第一型功函数金属层的堆叠。 阻挡金属层可以直接沉积在栅极介电层上。 图案化第一型功函数金属层仅存在于第一类场效应晶体管的区域中。 第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的势垒金属层上。 或者，第一类功函数层可以直接沉积在栅介电层上。 图案化阻挡金属层仅存在于第一类场效应晶体管的区域中。 第二类型功函数金属层直接沉积在第二类场效应晶体管的区域中的栅介质层上。 导电材料填充和平坦化形成双功能功能替代栅极结构。

    Fabrication of higher-k dielectrics
    17.
    发明授权
    Fabrication of higher-k dielectrics 有权
    高k电介质的制备

    公开(公告)号：US09478425B1

    公开(公告)日：2016-10-25

    申请号：US15045474

    申请日：2016-02-17

    申请人： International Business Machines Corporation

    发明人： Michael P. Chudzik ,  Min Dai ,  Dominic J. Schepis ,  Shahab Siddiqui

    IPC分类号： H01L21/8238 ,  H01L21/283 ,  H01L21/324

    CPC分类号： H01L21/823857 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.

    摘要翻译： 一种制造半导体结构的方法，以及所得结构。 该方法包括在衬底上形成氧化物层。 该方法包括在氧化物层上形成金属层。 该方法包括在金属层上方形成第一覆盖层。 形成第一覆盖层的材料可以是氧化钛或氮氧化钛。 该方法包括退火半导体结构。 退火半导体结构可能导致金属从金属层扩散到氧化物层中。

    HIGH DENSITY FINFET DEVICES WITH UNMERGED FINS
    20.
    发明申请
    HIGH DENSITY FINFET DEVICES WITH UNMERGED FINS 审中-公开
    高密度FINFET器件与未知的FINS

    公开(公告)号：US20150333145A1

    公开(公告)日：2015-11-19

    申请号：US14278674

    申请日：2014-05-15

    申请人： International Business Machines Corporation

    发明人： Michael P. Chudzik ,  Brian J. Greene ,  Edward P. Maciejewski ,  Kevin McStay ,  Shreesh Narasimha ,  Chengwen Pei ,  Werner A. Rausch

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

    摘要： Embodiments of the present invention provide a finFET and method of fabrication to achieve advantages of both merged and unmerged fins. A first step of epitaxy is performed with either partial diamond or full diamond growth. This is followed by a second step of deposition of a semiconductor cap region on the finFET source/drain area using a directional deposition process, followed by an anneal to perform Solid Phase Epitaxy or poly recrystalization. As a result, the fins remain unmerged, but the epitaxial volume is increased to provide reduced contact resistance. Embodiments of the present invention allow a narrower fin pitch, which enables increased circuit density on an integrated circuit.

    摘要翻译： 本发明的实施例提供了finFET和制造方法，以实现合并和非鳍片翅片的优点。 用部分金刚石或全金刚石生长进行外延的第一步。 随后是使用定向沉积工艺在finFET源/漏区上沉积半导体盖区域，随后进行退火以进行固相外延或多重重结晶的第二步骤。 结果，翅片保持未熔化，但外延体积增加以提供降低的接触电阻。 本发明的实施例允许更窄的翅片间距，其能够增加集成电路上的电路密度。