公开(公告)号：US20240063203A1

公开(公告)日：2024-02-22

申请号：US17889962

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Navneet SINGH ,  Sushil PADMANABHAN ,  Samarth ALVA

IPC: H01L25/18 ,  H01L23/15 ,  H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/481 ,  H01L23/5384 ,  H01L21/486 ,  H01L21/4857 ,  H01L25/50 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass, and buildup layers over the first substrate. In an embodiment, a first die is over the buildup layers, a second die is over the buildup layers and adjacent to the first die, and where conductive routing in the buildup layers electrically couples the first die to the second die.

公开(公告)号：US20240063127A1

公开(公告)日：2024-02-22

申请号：US17889238

申请日：2022-08-16

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/13 ,  H01L23/15 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/13 ,  H01L23/15 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/152 ,  H01L2924/15788 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate with a cavity, where the first substrate comprises glass. In an embodiment, a second substrate is in the cavity. In an embodiment, a bond film covers a bottom of the second substrate and extends up sidewalls of the second substrate.

公开(公告)号：US20230087810A1

公开(公告)日：2023-03-23

申请号：US17482852

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD ,  Oscar OJEDA ,  Bai NIE ,  Brandon C. MARIN ,  Gang DUAN ,  Jacob VEHONSKY ,  Onur OZKAN ,  Nicholas S. HAEHN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

公开(公告)号：US20230085944A1

公开(公告)日：2023-03-23

申请号：US17482843

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Bai NIE ,  Brandon C. MARIN ,  Sandeep B. SANE ,  Leonel ARANA ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a core, where the core comprises an organic material. In an embodiment, a via is provided through a thickness of the core. In an embodiment, a shell is around the via, where the shell comprises a magnetic material. In an embodiment, a mold layer is over the core, and a bridge is embedded in the mold layer. In an embodiment, a column is through the mold layer, where the column is aligned with the via.

公开(公告)号：US20220190918A1

公开(公告)日：2022-06-16

申请号：US17119844

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Kaveh HOSSEINI ,  Conor O'KEEFFE ,  Hiroki TANAKA

IPC: H04B10/2581 ,  H04B10/50 ,  H04B10/66 ,  G02F1/09 ,  G02F1/01 ,  G02B27/28

Abstract: Embodiments disclosed herein include photonics systems with a dual polarization module. In an embodiment, a photonics patch comprises a patch substrate, and a photonics die over a first surface of the patch substrate. In an embodiment, a multiplexer is over a second surface of the patch substrate. In an embodiment, a first optical path from the photonics die to the multiplexer is provided for propagating a first optical signal, and a second optical path from the photonics die to the multiplexer is provided for propagating a second optical signal. In an embodiment, a Faraday rotator is provided along the second optical path to convert the second optical signal from a first mode to a second mode before reaching the multiplexer.

公开(公告)号：US20250107112A1

公开(公告)日：2025-03-27

申请号：US18371294

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas PIETAMBARAM ,  Mohammad Mamunur RAHMAN ,  Sashi Shekhar KANDANUR ,  Aleksandar ALEKSOV ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI

IPC: H01L23/48 ,  H01L23/498

Abstract: Coaxial magnetic inductor structures useful for semiconductor packaging applications are provided. The coaxial magnetic inductors can be located in semiconductor package cores and the semiconductor package cores can be, for example, comprised of an amorphous solid glass material. Methods of manufacturing a coaxial magnetic inductors in a package substrate core are also provided.

公开(公告)号：US20240339412A1

公开(公告)日：2024-10-10

申请号：US18130584

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Cary KULIASHA ,  Brandon C. MARIN ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM

IPC: H01L23/538 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L23/645 ,  H01L25/0655 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2924/1511

Abstract: Embodiments disclosed herein include an interconnect bridge. In an embodiment, the interconnect bridge comprises a substrate, and a first trace on the substrate. In an embodiment, a first layer is on the first trace, where the first layer comprises a magnetic material. In an embodiment, a second layer is over the substrate, where the second layer comprises an insulating material. In an embodiment, a second trace is embedded in the second layer.

公开(公告)号：US20240312853A1

公开(公告)日：2024-09-19

申请号：US18121331

申请日：2023-03-14

Applicant: Intel Corporation

Inventor： Sashi S. KANDANUR ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Brandon C. MARIN ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Gang DUAN ,  Mohammad Mamunur RAHMAN ,  Numair AHMED

IPC: H01L23/15 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20240243088A1

公开(公告)日：2024-07-18

申请号：US18622486

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Jacob VEHONSKY

IPC: H01L23/00 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

CPC classification number: H01L24/14 ,  C25D3/38 ,  C25D5/022 ,  C25D7/12 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/1403

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.

公开(公告)号：US20240177918A1

公开(公告)日：2024-05-30

申请号：US18071237

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Mohammad Mamunur RAHMAN

IPC: H01F27/28 ,  H01F27/30 ,  H01F41/04 ,  H01L23/08 ,  H01L23/31

CPC classification number: H01F27/2804 ,  H01F27/306 ,  H01F41/041 ,  H01L23/08 ,  H01L23/3128 ,  H01F2027/2809 ,  H01F2027/2819

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate, a first opening through the core substrate, a second opening through the core substrate and adjacent to the first opening, and a first structure around the core substrate between the first opening and the second opening. In an embodiment, the first structure is electrically conductive. The package core may further comprise a second structure around the core substrate outside of the first opening and the second opening, where the second structure is electrically conductive.