公开(公告)号：US10411001B2

公开(公告)日：2019-09-10

申请号：US15781798

申请日：2015-12-16

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10

摘要： Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (TC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.

公开(公告)号：US09960224B2

公开(公告)日：2018-05-01

申请号：US15282504

申请日：2016-09-30

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Jiun Hann Sir ,  Han Kung Chua ,  Min Suet Lim ,  Hoay Tien Teoh

IPC分类号： H01L49/02

CPC分类号： H01L28/75

摘要： A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.

公开(公告)号：US09907170B2

公开(公告)日：2018-02-27

申请号：US15037856

申请日：2015-07-01

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H01R12/70 ,  H01R12/78 ,  H05K1/14 ,  H05K1/02

CPC分类号： H05K1/14 ,  H01R12/7058 ,  H01R12/77 ,  H01R12/78 ,  H01R12/88 ,  H05K1/028 ,  H05K2201/10037 ,  H05K2201/10356

摘要： A computer system assembly that includes a substrate and a first board mounted on the substrate. A flexible cable is secured to the first board. The computer system assembly further includes a second board mounted on the substrate. The second board includes a FPC connector. The FPC connector includes a body having a channel extending through the body such that the flexible cable may be positioned in the channel and pulled entirely through the body of the FPC connector. The FPC connector further includes a latching mechanism that secures the flexible cable within the channel once the flexible cable is pulled through the FPC connector. The first board and the second board are moved closer together as the flex cable is pulled through the FPC connector before at least one of the first board and the second board is mounted on the substrate.

公开(公告)号：US10785872B2

公开(公告)日：2020-09-22

申请号：US16263370

申请日：2019-01-31

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H05K1/11 ,  H05K1/02 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

摘要： A jumper may be adapted to transmit an electrical signal. The jumper may be included in a system on a chip. The system on a chip may include a substrate, and the substrate may include one or more routing layers. The jumper may be included in the one or more routing layers of the substrate. A first interconnect may be positioned on a first side of the system on a chip, and a second interconnect may be positioned on a second side of the system on a chip. The jumper may be in electrical communication with the first interconnect, and may be in electrical communication with the second interconnect. The jumper may be electrically isolated from other components of the system on a chip, such as one or more die coupled to the substrate.

公开(公告)号：US10163777B2

公开(公告)日：2018-12-25

申请号：US15476905

申请日：2017-03-31

申请人： INTEL CORPORATION

发明人： Seok Ling Lim ,  Eng Huat Goh ,  Hoay Tien Teoh ,  Jenny Shio Yin Ong ,  Jia Yan Go ,  Jiun Hann Sir ,  Min Suet Lim

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/043

摘要： Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect element on the logic board, the conductive interconnect element to connect the decoupling capacitor on the logic board to a power conductor comprising a power pad of a semiconductor package, the conductive interconnect element at a different layer than a ground-potential layer of the logic board. Other embodiments are described and claimed.

公开(公告)号：US20180324951A1

公开(公告)日：2018-11-08

申请号：US15774863

申请日：2015-11-13

申请人： Intel Corporation

发明人： Penang Goh ,  Hoay Tien Teoh ,  Jia Yan Go ,  Jenny Shio Yin Ong

IPC分类号： H05K1/18 ,  H05K3/34

CPC分类号： H05K1/181 ,  H01L25/105 ,  H01L2224/81203 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/34 ,  H05K3/3436 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/613

摘要： The electronic assembly includes a printed circuit board; an electronic package that includes an electronic component mounted on a substrate, wherein the substrate is mounted to the printed circuit board; a first memory module mounted to the printed circuit board such that the first memory module is adjacent to the electronic package; a second memory module mounted to the printed circuit board; and a substrate bridge that electrically connects the first and second memory modules to the electronic package, wherein a lower surface of the substrate bridge is connected to an upper surface of the substrate and an upper surface of the first and second memory modules.

公开(公告)号：US20180097056A1

公开(公告)日：2018-04-05

申请号：US15282504

申请日：2016-09-30

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Jiun Hann Sir ,  Han Kung Chua ,  Min Suet Lim ,  Hoay Tien Teoh

IPC分类号： H01L49/02

CPC分类号： H01L28/75

摘要： A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.

公开(公告)号：US20160118354A1

公开(公告)日：2016-04-28

申请号：US14986542

申请日：2015-12-31

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L24/02 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/0105 ,  H01L2224/05552 ,  H01L2924/00

摘要： A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

摘要翻译： 一种微电子封装，其具有邻近微电子器件的有源表面和侧面的第一无凸起的构建层结构和邻近微电子器件的后表面的第二无扰动积聚层结构，其中通过第一无扰动构建形成导电路径 从微电子器件有源表面到第二无扰性积聚层结构中的导电路径的上层，并且其中邻近微电子器件背表面并延伸到微电子器件中的穿硅通孔电连接到第二无扰动积聚层 结构导电路线。