公开(公告)号：US12058849B2

公开(公告)日：2024-08-06

申请号：US17522225

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Kinyip Phoa ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Uygar E. Avci ,  Rajesh Kumar

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02

CPC classification number: H10B12/312 ,  H01L28/60 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78696

Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.

公开(公告)号：US12057491B2

公开(公告)日：2024-08-06

申请号：US16239090

申请日：2019-01-03

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Dax M. Crum ,  Stephen M. Cea ,  Leonard P. Guler ,  Tahir Ghani

IPC: H01L27/12 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6653 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7853

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

公开(公告)号：US12051698B2

公开(公告)日：2024-07-30

申请号：US17030350

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Daniel G. Ouellette ,  Daniel B. O'Brien ,  Jeffrey S. Leib ,  Orb Acton ,  Lukas Baumgartel ,  Dan S. Lavric ,  Dax M. Crum ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L27/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/408 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.

公开(公告)号：US12029021B2

公开(公告)日：2024-07-02

申请号：US17701419

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Peng Zheng ,  Varun Mishra ,  Tahir Ghani

IPC: H10B10/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545

Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.

公开(公告)号：US12002810B2

公开(公告)日：2024-06-04

申请号：US16146800

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Dax M. Crum ,  Biswajeet Guha ,  Leonard Guler ,  Tahir Ghani

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.

公开(公告)号：US11991873B2

公开(公告)日：2024-05-21

申请号：US18109780

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Yu-Wen Huang ,  Shu Zhou

IPC: H10B12/00

CPC classification number: H10B12/03 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US20240113104A1

公开(公告)日：2024-04-04

申请号：US17936952

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Tahir Ghani ,  Xinning Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203

Abstract: Techniques are provided to form semiconductor devices that include a gate cut that passes through a plurality of semiconductor bodies (e.g., nanoribbons or nanosheets) such that the gate cut acts as a dielectric spine in a forksheet arrangement with the semiconductor bodies on either side of the gate cut. In an example, two semiconductor devices in a forksheet arrangement include semiconductor bodies directly on either side of a dielectric spine. A gate structure includes a gate dielectric (e.g., high-k gate dielectric material) and a gate electrode (e.g., conductive material such as workfunction material and/or gate fill metal) that extends around each of the semiconductor bodies of both semiconductor devices. The dielectric spine interrupts the entire height of the gate structure between the two devices and includes dielectric material (e.g., low-k dielectric), and the gate dielectric of the gate structure is not present along sidewalls of the spine between adjacent bodies.

公开(公告)号：US20240107749A1

公开(公告)日：2024-03-28

申请号：US17935639

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Sagar Suthram

IPC: H01L27/108 ,  G11C5/02 ,  G11C11/404

CPC classification number: H01L27/10829 ,  G11C5/025 ,  G11C11/4045

Abstract: Various arrangements for IC devices implementing memory with one access transistor for multiple capacitors are disclosed. An example IC device includes a memory array of M memory units, where each memory unit includes an access transistor and N capacitors coupled to the access transistor. A portion of the capacitors are formed in one or more layers above the access transistor, and a portion of the capacitors are formed in one or more layers below the access transistor. The capacitors in a particular memory unit may be coupled to a single via or to individual vias. In some embodiments, some of the vias are backside vias.

公开(公告)号：US20240105811A1

公开(公告)日：2024-03-28

申请号：US17955209

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Tahir Ghani ,  Anand Murthy ,  Wilfred Gomes ,  Pushkar Ranade

IPC: H01L29/51 ,  H01L21/28 ,  H01L27/11507 ,  H01L27/1159

CPC classification number: H01L29/516 ,  H01L27/11507 ,  H01L27/1159 ,  H01L29/40111 ,  G11C11/221

Abstract: An integrated circuit (IC) die includes a plurality of ferroelectric tunnel junction (FTJ) devices, where at least one FTJ of the plurality of FTJ devices comprises first electrode, a second electrode, ferroelectric material disposed between the first and second electrodes, and interface material disposed between at least one of the first and second electrodes and the ferroelectric material. Other embodiments are disclosed and claimed.

公开(公告)号：US20240105585A1

公开(公告)日：2024-03-28

申请号：US17955245

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Pushkar Ranade ,  Tahir Ghani ,  Wilfred Gomes ,  Sagar Suthram ,  Anand Murthy

IPC: H01L23/522 ,  H01L23/427

CPC classification number: H01L23/5223 ,  H01L23/427

Abstract: An embodiment of a capacitor in the back-side layers of an IC die may comprise any type of solid-state electrolyte material disposed between electrodes of the capacitor. Another embodiment of a capacitor anywhere in an IC die may include one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride between electrodes of the capacitor. Other embodiments are disclosed and claimed.