公开(公告)号：US09275954B2

公开(公告)日：2016-03-01

申请号：US14507328

申请日：2014-10-06

Applicant: Intermolecular, Inc.

Inventor： Tony P. Chiang ,  Majid Keshavarz ,  David E. Lazovsky

IPC: H01L21/31 ,  H01L23/532 ,  B82Y30/00 ,  H01L21/768 ,  H01L29/06 ,  H01L49/02

CPC classification number: H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

公开(公告)号：US20150287616A1

公开(公告)日：2015-10-08

申请号：US14725192

申请日：2015-05-29

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  Tony P. Chiang ,  Alexander Gorer ,  David E. Lazovsky

IPC: H01L21/67 ,  C23C16/455 ,  H01J37/32 ,  C23C16/46 ,  C23C16/52 ,  C23C16/44 ,  C23C16/458

CPC classification number: H01L21/67011 ,  C23C14/54 ,  C23C16/4412 ,  C23C16/45544 ,  C23C16/4557 ,  C23C16/45578 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/52 ,  H01J37/32449 ,  H01J37/32513 ,  H01J37/32724 ,  H01J2237/166 ,  H01J2237/20228 ,  H01J2237/20235 ,  H01L21/6715 ,  H01L21/76849 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/907 ,  Y10S438/913 ,  Y10T137/8593 ,  H01L2924/00

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract translation: 本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。 通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

公开(公告)号：US20140227871A1

公开(公告)日：2014-08-14

申请号：US14257694

申请日：2014-04-21

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  David E. Lazovsky ,  Sandra G. Malhotra

IPC: H01L21/768

CPC classification number: H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract translation: 在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料 在电介质区域。 可以选择性地在导电区域或非选择性地形成覆盖层; 在任一种情况下，形成在电介质区域上的覆盖层材料随后可以被去除，从而确保覆盖层材料仅在导电区域上形成。 硅烷类材料可用于形成掩模层。 覆盖层可以由导电材料，半导体材料或绝缘材料形成，并且可以使用包括常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积的任何适当的工艺形成。

公开(公告)号：US20140177315A1

公开(公告)日：2014-06-26

申请号：US13721279

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

Inventor： Dipankar Pramanik ,  David E. Lazovsky ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C11/56 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/145 ,  H01L45/1608

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Abstract translation: 提供了用于多位数据存储的电阻器阵列，而不需要增加存储器芯片的尺寸或缩小存储器芯片中包含的存储器单元的特征尺寸。 电阻器阵列包括多个离散电阻元件，以便以不同的串联组合方式连接到至少一个存储器单元或存储器件。 在一种配置中，通过将每个存储器单元或设备连接至少一个电阻器阵列，在连接的存储器件的电阻式开关存储器元件中发现的电阻式开关层能够处于多个电阻状态，用于存储多位数字信息。 在器件编程操作期间，当选择电阻器阵列内的电阻元件的期望的串联组合时，连接的存储器件中的电阻式开关层可以处于期望的电阻状态。

公开(公告)号：US08575036B2

公开(公告)日：2013-11-05

申请号：US13676981

申请日：2012-11-14

Applicant: Intermolecular, Inc.

Inventor： David E. Lazovsky ,  Thomas R. Boussie ,  Sandra G. Malhotra

IPC: H01L21/768

CPC classification number: H01L21/76829 ,  B82Y30/00 ,  H01L21/02183 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76849

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during formation of a capping layer on electrically conductive regions that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; capping layer material formed over the dielectric region can be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract translation: 在电子器件的电介质区域上形成掩模层，使得在由电介质区域分离的导电区域上形成覆盖层时，掩模层阻止在电介质区域上或电介质区域中形成覆盖层材料。 可以选择性地在导电区域或非选择性地形成覆盖层; 可以去除在电介质区域上形成的覆盖层材料，从而确保仅在导电区域上形成覆盖层材料。 可以使用诸如硅烷基SAM之类的硅烷基材料来形成掩模层。 覆盖层可以由半导体材料或电绝缘材料的导电材料形成，并且可以使用任何适当的工艺形成，包括常规沉积工艺，例如无电沉积，化学气相沉积，物理气相沉积或原子层沉积 。

公开(公告)号：US20130244425A1

公开(公告)日：2013-09-19

申请号：US13892516

申请日：2013-05-13

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  David E. Lazovsky ,  Sandra G. Malhotra

IPC: H01L21/768

CPC classification number: H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

公开(公告)号：US20130072026A1

公开(公告)日：2013-03-21

申请号：US13676981

申请日：2012-11-14

Applicant: INTERMOLECULAR, INC.

Inventor： David E. Lazovsky ,  Thomas R. Boussie ,  Sandra G. Malhotra

IPC: H01L21/768

CPC classification number: H01L21/76829 ,  B82Y30/00 ,  H01L21/02183 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76849

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during formation of a capping layer on electrically conductive regions that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; capping layer material formed over the dielectric region can be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract translation: 在电子器件的电介质区域上形成掩模层，使得在由电介质区域分离的导电区域上形成覆盖层时，掩模层阻止在电介质区域上或电介质区域中形成覆盖层材料。 可以选择性地在导电区域或非选择性地形成覆盖层; 可以去除在电介质区域上形成的覆盖层材料，从而确保仅在导电区域上形成覆盖层材料。 可以使用诸如硅烷基SAM之类的硅烷基材料来形成掩模层。 覆盖层可以由半导体材料或电绝缘材料的导电材料形成，并且可以使用任何适当的工艺形成，包括常规沉积工艺，例如无电沉积，化学气相沉积，物理气相沉积或原子层沉积 。

公开(公告)号：US20150310910A1

公开(公告)日：2015-10-29

申请号：US14627760

申请日：2015-02-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Dipankar Pramanik ,  David E. Lazovsky ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: G11C11/56 ,  G11C13/00

CPC classification number: G11C11/56 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/145 ,  H01L45/1608

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Abstract translation: 提供了用于多位数据存储的电阻器阵列，而不需要增加存储器芯片的尺寸或缩小存储器芯片中包含的存储器单元的特征尺寸。 电阻器阵列包括多个离散电阻元件，以便以不同的串联组合方式连接到至少一个存储器单元或存储器件。 在一种配置中，通过将每个存储器单元或设备连接至少一个电阻器阵列，在连接的存储器件的电阻式开关存储器元件中发现的电阻式开关层能够处于多个电阻状态，用于存储多位数字信息。 在器件编程操作期间，当选择电阻器阵列内的电阻元件的期望的串联组合时，连接的存储器件中的电阻式开关层可以处于期望的电阻状态。

公开(公告)号：US09076716B2

公开(公告)日：2015-07-07

申请号：US14077137

申请日：2013-11-11

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  Tony P. Chiang ,  Alexander Gorer ,  David E. Lazovsky

IPC: C40B50/00 ,  H01L21/66 ,  C23C14/54 ,  C23C16/52 ,  H01L21/67 ,  H01L21/768

CPC classification number: H01L21/67011 ,  C23C14/54 ,  C23C16/4412 ,  C23C16/45544 ,  C23C16/4557 ,  C23C16/45578 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/52 ,  H01J37/32449 ,  H01J37/32513 ,  H01J37/32724 ,  H01J2237/166 ,  H01J2237/20228 ,  H01J2237/20235 ,  H01L21/6715 ,  H01L21/76849 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/907 ,  Y10S438/913 ,  Y10T137/8593 ,  H01L2924/00

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract translation: 本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。 通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

公开(公告)号：US20150179500A1

公开(公告)日：2015-06-25

申请号：US14625488

申请日：2015-02-18

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  David E. Lazovsky ,  Sandra G. Malhotra

IPC: H01L21/768 ,  H01L21/288 ,  H01L21/02 ,  H01L21/31

CPC classification number: H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract translation: 在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料 在电介质区域。 可以选择性地在导电区域或非选择性地形成覆盖层; 在任一种情况下，形成在电介质区域上的覆盖层材料随后可以被去除，从而确保覆盖层材料仅在导电区域上形成。 硅烷类材料可用于形成掩模层。 覆盖层可以由导电材料，半导体材料或绝缘材料形成，并且可以使用包括常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积的任何适当的工艺形成。