公开(公告)号：US20120126937A1

公开(公告)日：2012-05-24

申请号：US13296242

申请日：2011-11-15

申请人： Lawrence A. Clevenger ,  Rainer K. Krause ,  Kevin S. Petrarca ,  Carl J. Radens ,  Brian C. Sapp

发明人： Lawrence A. Clevenger ,  Rainer K. Krause ,  Kevin S. Petrarca ,  Carl J. Radens ,  Brian C. Sapp

IPC分类号： G08B29/00

CPC分类号： G08B13/14 ,  G06Q10/087

摘要： Asset management for control of electric appliances comprises a keycode unit and an equipment unit embedded in an appliance. The keycode unit is located in a protected environment and relates to an asset management area. The equipment unit may store an appliance identification code. The keycode unit and the equipment unit may be in communication contact, whereby the equipment unit sends positioning coordinates to the keycode unit, and wherein the equipment unit is adapted to lock the appliance via the lock unit, in response to a lock signal that the equipment unit receives from the keycode unit, if the appliance moves outside the asset management area.

摘要翻译： 用于控制电器的资产管理包括密码单元和嵌入在器具中的设备单元。 键码单元位于受保护的环境中，与资产管理区域有关。 设备单元可以存储设备标识码。 键码单元和设备单元可以是通信接触的，由此设备单元向键码单元发送定位坐标，并且其中设备单元适于经由锁定单元锁定设备，响应于锁定信号，设备 如果设备移动到资产管理区域外，则单元从密钥单元接收。

公开(公告)号：US08026166B2

公开(公告)日：2011-09-27

申请号：US12190131

申请日：2008-08-12

申请人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-sang Oh

发明人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-sang Oh

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.

摘要翻译： 提供包括具有低介电常数和良好氧阻隔性能的封盖层的互连结构及其制备方法。 在一个实施例中，集成电路结构包括：设置在半导体衬底之上的层间电介质层; 嵌入在所述层间电介质层中的导电互连; 包括设置在所述导电互连上的SiwCxNyHz的第一覆盖层; 包含设置在第一覆盖层上的介电常数小于约4的SiaCbNcHd（具有较小的N）的第二覆盖层; 以及第三覆盖层，其包括设置在所述第二覆盖层上的SiwCxNyHz，其中a + b + c + d = 1.0和a，b，c和d各自大于0且小于1，并且其中w + x + y + z = 1.0，w，x，y和z分别大于0且小于1。

公开(公告)号：US20110221062A1

公开(公告)日：2011-09-15

申请号：US12721032

申请日：2010-03-10

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Satyanarayana V. Nitta ,  Anthony D. Lisi ,  Qinghuang Lin

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Satyanarayana V. Nitta ,  Anthony D. Lisi ,  Qinghuang Lin

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/4821 ,  C08L83/04 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地说，本文描述的方法提供内置于光可图案化的低k材料中的互连结构，其中通过光刻法在光可图案化的低k材料中限定气隙。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US07989291B2

公开(公告)日：2011-08-02

申请号：US12712369

申请日：2010-02-25

申请人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

发明人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

IPC分类号： H01L29/72

CPC分类号： H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.

摘要翻译： 在基板上形成具有线性边缘的突出结构。 突出结构可以是场效应晶体管的栅极线。 应力产生衬垫沉积在衬底上。 含有至少两种不混溶的聚合物嵌段组分的非感光性自组装嵌段共聚物层沉积在应力产生衬里上，并进行退火以允许不相容的组分相分离。 聚合物抗蚀剂被显影以除去至少两个聚合物嵌段组分中的至少一个，其由于突出结构的线性边缘而形成嵌套线的图案。 在自对准和自组装的聚合物抗蚀剂中形成线性纳米级条纹。 将应力产生层图案化成具有亚光刻宽度的线性应力产生条纹。 线性应力产生条纹沿其长度方向提供主要的单轴应力，向下面的半导体器件提供各向异性的应力。

公开(公告)号：US20110100412A1

公开(公告)日：2011-05-05

申请号：US12825649

申请日：2010-06-29

申请人： Lawrence A. Clevenger ,  Rainer Krause ,  Karl-Heinz Lehnert ,  Gerd Pfeiffer ,  Kevin Prettyman

发明人： Lawrence A. Clevenger ,  Rainer Krause ,  Karl-Heinz Lehnert ,  Gerd Pfeiffer ,  Kevin Prettyman

IPC分类号： H01L31/042 ,  H01L31/18

CPC分类号： H01L31/1868 ,  H01L31/02167 ,  H01L31/02168 ,  H01L31/0236 ,  H01L31/0508 ,  H01L31/1804 ,  H01L31/1864 ,  H02S50/10 ,  Y02E10/547 ,  Y02P70/521

摘要： A photovoltaic module and a method of manufacturing such a module in which metal is deposited in a pattern on the front side of a semiconductor wafer which acts as an electrode. Photovoltaic cells manufactured using a semiconductor wafer typically have a P type semiconductor region and an N type semiconductor region. The metal on the front side of each of the photovoltaic cells forms an electrical connection to the doped layer of the semiconductor wafer on its front side.

摘要翻译： 一种光伏模块及其制造方法，其中金属以图案形式沉积在用作电极的半导体晶片的正面上。 使用半导体晶片制造的光伏电池通常具有P型半导体区域和N型半导体区域。 每个光伏电池的前侧上的金属在其前侧形成与半导体晶片的掺杂层的电连接。

公开(公告)号：US07906428B2

公开(公告)日：2011-03-15

申请号：US12121216

申请日：2008-05-15

申请人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

公开(公告)号：US07888729B2

公开(公告)日：2011-02-15

申请号：US12198345

申请日：2008-08-26

申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu

发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/66825

摘要： A first portion of a semiconductor substrate belonging to a flash memory device region is recessed to a recess depth to form a recessed region, while a second portion of the semiconductor substrate belonging to a logic device region is protected with a masking layer. A first gate dielectric layer and a first gate conductor layer formed within the recessed region such that the first gate conductive layer is substantially coplanar with the top surfaces of the shallow trench isolation structures. A second gate dielectric layer, a second gate conductor layer, and a gate cap hard mask layer, each having a planar top surface, is subsequently patterned. The pattern of the gate structure in the flash memory device region is transferred into the first gate conductor layer and the first gate dielectric layer to form a floating gate and a first gate dielectric, respectively.

摘要翻译： 属于闪存器件区域的半导体衬底的第一部分凹陷到凹陷深度以形成凹陷区域，而属于逻辑器件区域的半导体衬底的第二部分被掩蔽层保护。 形成在凹陷区域内的第一栅介质层和第一栅极导体层，使得第一栅极导电层与浅沟槽隔离结构的顶表面基本共面。 随后对第二栅介质层，第二栅极导体层和栅帽硬掩模层进行构图，每个具有平坦的顶表面。 闪存器件区域中的栅极结构的图案被转移到第一栅极导体层和第一栅极介电层中，以分别形成浮置栅极和第一栅极电介质。

公开(公告)号：US20100317148A1

公开(公告)日：2010-12-16

申请号：US12849648

申请日：2010-08-03

申请人： Lawrence A. Clevenger ,  Harold J. Hovel ,  Rainer K. Krause ,  Kevin M. Prettyman

发明人： Lawrence A. Clevenger ,  Harold J. Hovel ,  Rainer K. Krause ,  Kevin M. Prettyman

IPC分类号： H01L31/18

CPC分类号： H01L31/022433 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  Y02E10/50

摘要： Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature.

摘要翻译： 用于制造用于光伏电池的接触栅极的方法通常包括提供具有设置在面向太阳侧的抗反射涂层的光伏电池，所述光伏电池包括具有p-n结的硅衬底; 将UV敏感的光致抗蚀剂和/或聚合物的图案软化到抗反射涂层上; 将UV敏感的光致抗蚀剂和/或聚合物暴露于紫外线辐射以固化UV敏感的光致抗蚀剂和/或聚合物; 蚀刻图案以在防反射涂层中形成限定接触网格的开口; 剥离UV敏感的光致抗蚀剂和/或聚合物; 以及将导电金属沉积到由图案限定的开口中。 金属基糊料可以是铝基，其可以在相对低的温度下退火。

公开(公告)号：US07790601B1

公开(公告)日：2010-09-07

申请号：US12561651

申请日：2009-09-17

申请人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

发明人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/31111 ,  H01L21/31144

摘要： Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.

摘要翻译： 公开了一种在互连中形成气隙的积分方法的过程。 在半导体衬底上的金属布线层的顶部上沉积介电覆盖层，接着是牺牲介电层和图案转移层。 图案通过图案转移层，牺牲介电层，电介质盖层转移到金属布线层中。 牺牲介电层的存在有助于控制电介质盖层的厚度和轮廓，这进而影响互连的可靠性。

公开(公告)号：US07692308B2

公开(公告)日：2010-04-06

申请号：US12256735

申请日：2008-10-23

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.

摘要翻译： 电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。