利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

66 条记录 (耗时 0.024 秒)

    Three-dimensional semiconductor memory devices
    11.
    发明授权
    Three-dimensional semiconductor memory devices 有权
    三维半导体存储器件

    公开(公告)号：US08598647B2

    公开(公告)日：2013-12-03

    申请号：US13291519

    申请日：2011-11-08

    申请人： Dongwoo Kim ,  Toshiro Nakanishi ,  SeungHyun Lim ,  Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn

    发明人： Dongwoo Kim ,  Toshiro Nakanishi ,  SeungHyun Lim ,  Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided are three-dimensional semiconductor devices. The device includes conductive patterns stacked on a substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern includes a first doped region disposed adjacent to at least one of the conductive patterns, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

    摘要翻译： 提供三维半导体器件。 该器件包括堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案包括邻近至少一个导电图案设置的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

    Nonvolatile memory device and method of forming the same
    17.
    发明授权
    Nonvolatile memory device and method of forming the same 有权
    非易失存储器件及其形成方法

    公开(公告)号：US08420482B2

    公开(公告)日：2013-04-16

    申请号：US12458732

    申请日：2009-07-21

    申请人： Juwan Lim ,  Sungkweon Baek ,  Kwangmin Park ,  Seungjae Baik ,  Kihyun Hwang

    发明人： Juwan Lim ,  Sungkweon Baek ,  Kwangmin Park ,  Seungjae Baik ,  Kihyun Hwang

    IPC分类号： H01L21/8247

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

    摘要翻译： 一种非易失性存储器件和一种形成非易失性存储器件的方法，所述方法包括在衬底上形成隧道绝缘层，其中形成隧道绝缘层包括通过以下处理形成多元件绝缘层，所述工艺包括：顺序地提供第一元件源 ，第二元件源和第三元件源，在隧道绝缘层上形成电荷存储层，在电荷存储层上形成阻挡绝缘层，并在阻挡绝缘层上形成控制栅电极。

    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    18.
    发明申请
    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US20120267701A1

    公开(公告)日：2012-10-25

    申请号：US13425584

    申请日：2012-03-21

    申请人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

    发明人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/1157

    摘要： Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.

    摘要翻译： 非易失性存储器件包括垂直堆叠的非易失性存储单元。 非易失性存储单元的垂直堆叠包括其中具有第一栅极图案的第一非易失性存储单元，其通过具有第一厚度的第一多层电介质图案与垂直有源区域分离，并且具有第二非易失性存储单元的第二非易失性存储单元 栅极图案，其通过具有第二厚度的第二多层电介质图案与垂直有源区域分离。 第二栅极图案也从第一栅极图案分离小于第一和第二厚度之和的距离。

    Semiconductor memory device having insulation patterns and cell gate patterns
    19.
    发明授权
    Semiconductor memory device having insulation patterns and cell gate patterns 有权
    具有绝缘图案和单元栅极图案的半导体存储器件

    公开(公告)号：US08084819B2

    公开(公告)日：2011-12-27

    申请号：US12650137

    申请日：2009-12-30

    申请人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    发明人： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    IPC分类号： H01L27/01 ,  H01L21/4763

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

    摘要： Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

    摘要翻译： 提供半导体存储器件和形成半导体存储器件的方法。 所述方法可以包括形成交替层叠在基板上的绝缘层和单元栅极层，通过连续图案化通过单元栅极层和绝缘层形成开口，并且在开口中的单元栅极层的侧壁上选择性地形成导电阻挡层 。