利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

123 条记录 (耗时 0.041 秒)

    Semiconductor chips with reduced stress from underfill at edge of chip
    11.
    发明授权
    Semiconductor chips with reduced stress from underfill at edge of chip 有权
    半导体芯片在芯片边缘的底层填料中的应力减小

    公开(公告)号：US07871920B2

    公开(公告)日：2011-01-18

    申请号：US12762404

    申请日：2010-04-19

    申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    IPC分类号： H01L21/44

    CPC分类号： H01L23/3192 ,  H01L21/563 ,  H01L23/3178 ,  H01L2224/73203 ,  H01L2924/01079

    摘要： Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

    摘要翻译： 用于形成它的结构和方法。 半导体芯片包括半导体衬底和半导体衬底上的晶体管。 该芯片还包括在半导体衬底之上的N个互连层，并且电耦合到晶体管，N是正整数。 芯片还包括在N个互连层的顶部上的第一介电层，以及在第一介电层的顶部上的第二介电层。 第二电介质层与N互连层的每个互连层直接物理接触。 芯片还包括在第二电介质层顶部的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。 芯片还包括在底部填充层顶部的层压基板。 底部填充层被夹在第二介电层和层叠基板之间。

    SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP
    13.
    发明申请
    SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP 有权
    具有降低应力的半导体芯片

    公开(公告)号：US20100203685A1

    公开(公告)日：2010-08-12

    申请号：US12762404

    申请日：2010-04-19

    申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    IPC分类号： H01L21/56

    CPC分类号： H01L23/3192 ,  H01L21/563 ,  H01L23/3178 ,  H01L2224/73203 ,  H01L2924/01079

    摘要： Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

    摘要翻译： 用于形成它的结构和方法。 半导体芯片包括半导体衬底和半导体衬底上的晶体管。 该芯片还包括在半导体衬底之上的N个互连层，并且电耦合到晶体管，N是正整数。 芯片还包括在N个互连层的顶部上的第一介电层，以及在第一介电层的顶部上的第二介电层。 第二电介质层与N互连层的每个互连层直接物理接触。 芯片还包括在第二电介质层顶部的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。 芯片还包括在底部填充层顶部的层压基板。 底部填充层被夹在第二介电层和层叠基板之间。