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1.发明申请GAP CAPACITORS FOR MONITORING STRESS IN SOLDER BALLS IN FLIP CHIP TECHNOLOGY 有权用于监测飞利浦芯片技术中焊接棒应力的GAP电容器公开(公告)号：US20100203655A1
公开(公告)日：2010-08-12
申请号：US12765979
申请日：2010-04-23
申请人： Stephen P. Ayotte , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
发明人： Stephen P. Ayotte , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
CPC分类号： H01L23/5223 , H01L22/34 , H01L24/02 , H01L24/11 , H01L28/60 , H01L2224/0401 , H01L2224/1147 , H01L2224/13099 , H01L2224/16 , H01L2224/29116 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/30105 , Y10S438/957 , H01L2924/00
摘要： A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.
摘要翻译： 一种半导体结构的形成方法和操作方法。 该结构包括（i）电介质层，（ii）电介质层上的底部电容器板和导电线，（iii）底部电容器板顶部的顶部电容器板，（iv）间隙区域，以及 （v）电介质层上的焊球。 电介质层包括限定垂直于顶表面的参考方向的顶表面。 顶部电容器板在底部电容器板上沿参考方向重叠。 间隙区域夹在底部电容器板和顶部电容器板之间。 间隙区域不包括任何液体或固体材料。 焊球与导电线电连接。 顶部电容器板设置在电介质层和焊球之间。
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2.发明授权Gap capacitors for monitoring stress in solder balls in flip chip technology 失效用于在倒装芯片技术中监测焊球中的应力的间隙电容器公开(公告)号：US07709876B2
公开(公告)日：2010-05-04
申请号：US12028845
申请日：2008-02-11
申请人： Stephen P. Ayotte , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
发明人： Stephen P. Ayotte , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
IPC分类号： H01L27/108
CPC分类号： H01L23/5223 , H01L22/34 , H01L24/02 , H01L24/11 , H01L28/60 , H01L2224/0401 , H01L2224/1147 , H01L2224/13099 , H01L2224/16 , H01L2224/29116 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/30105 , Y10S438/957 , H01L2924/00
摘要： A semiconductor structure and a method for forming the same. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.
摘要翻译： 半导体结构及其形成方法。 该结构包括（i）电介质层，（ii）电介质层上的底部电容器板和导电线，（iii）底部电容器板顶部的顶部电容器板，（iv）间隙区域，以及 （v）电介质层上的焊球。 电介质层包括限定垂直于顶表面的参考方向的顶表面。 顶部电容器板在底部电容器板上沿参考方向重叠。 间隙区域夹在底部电容器板和顶部电容器板之间。 间隙区域不包括任何液体或固体材料。 焊球与导电线电连接。 顶部电容器板设置在电介质层和焊球之间。
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3.发明授权Gap capacitors for monitoring stress in solder balls in flip chip technology 有权用于在倒装芯片技术中监测焊球中的应力的间隙电容器公开(公告)号：US07939390B2
公开(公告)日：2011-05-10
申请号：US12765979
申请日：2010-04-23
申请人： Stephen P. Ayotte , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
发明人： Stephen P. Ayotte , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
IPC分类号： H01L21/338 , H01L21/8244
CPC分类号： H01L23/5223 , H01L22/34 , H01L24/02 , H01L24/11 , H01L28/60 , H01L2224/0401 , H01L2224/1147 , H01L2224/13099 , H01L2224/16 , H01L2224/29116 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/30105 , Y10S438/957 , H01L2924/00
摘要： A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.
摘要翻译： 一种半导体结构的形成方法和操作方法。 该结构包括（i）电介质层，（ii）电介质层上的底部电容器板和导电线，（iii）底部电容器板顶部的顶部电容器板，（iv）间隙区域，以及 （v）电介质层上的焊球。 电介质层包括限定垂直于顶表面的参考方向的顶表面。 顶部电容器板在底部电容器板上沿参考方向重叠。 间隙区域夹在底部电容器板和顶部电容器板之间。 间隙区域不包括任何液体或固体材料。 焊球与导电线电连接。 顶部电容器板设置在电介质层和焊球之间。
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4.发明申请GAP CAPACITORS FOR MONITORING STRESS IN SOLDER BALLS IN FLIP CHIP TECHNOLOGY 失效用于监测飞利浦芯片技术中焊接棒应力的GAP电容器公开(公告)号：US20090201626A1
公开(公告)日：2009-08-13
申请号：US12028845
申请日：2008-02-11
申请人： Stephen P. Ayotte , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
发明人： Stephen P. Ayotte , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
CPC分类号： H01L23/5223 , H01L22/34 , H01L24/02 , H01L24/11 , H01L28/60 , H01L2224/0401 , H01L2224/1147 , H01L2224/13099 , H01L2224/16 , H01L2224/29116 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/30105 , Y10S438/957 , H01L2924/00
摘要： A semiconductor structure and a method for forming the same. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.
摘要翻译： 半导体结构及其形成方法。 该结构包括（i）电介质层，（ii）电介质层上的底部电容器板和导电线，（iii）底部电容器板顶部的顶部电容器板，（iv）间隙区域，以及 （v）电介质层上的焊球。 电介质层包括限定垂直于顶表面的参考方向的顶表面。 顶部电容器板在底部电容器板上沿参考方向重叠。 间隙区域夹在底部电容器板和顶部电容器板之间。 间隙区域不包括任何液体或固体材料。 焊球与导电线电连接。 顶部电容器板设置在电介质层和焊球之间。
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公开(公告)号：US07547576B2
公开(公告)日：2009-06-16
申请号：US11275867
申请日：2006-02-01
申请人： Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
发明人： Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
IPC分类号： H01L21/00
CPC分类号： H01L24/13 , H01L23/562 , H01L24/11 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/056 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/15787 , H01L2924/00014 , H01L2924/00
摘要： A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
摘要翻译： 其形成结构及其方法。 半导体结构包括与第一半导体芯片直接物理接触的第一半导体芯片和N个焊料凸块，其中N是正整数。 半导体结构还包括在第一半导体芯片的周边上的第一焊料壁，使得第一焊料壁形成围绕N个焊料凸点的闭环。
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公开(公告)号：US07462509B2
公开(公告)日：2008-12-09
申请号：US11383595
申请日：2006-05-16
申请人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
CPC分类号： H01L24/10 , H01L23/13 , H01L23/481 , H01L23/49833 , H01L23/5385 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L2224/13 , H01L2224/13099 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H05K1/145 , H05K3/222 , H05K2201/10674 , Y10T436/171538 , Y10T436/172307 , H01L2924/00014 , H01L2924/00
摘要： An method of packaging an electronic device. The method for packaging the device including: providing a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.
摘要翻译： 一种封装电子设备的方法。 用于封装器件的方法包括：提供第一衬底，第二衬底和具有第一侧和相对第二侧的集成电路芯片，第一组芯片焊盘和第二组芯片焊盘， 集成电路芯片的第二侧，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的相应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。
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公开(公告)号：US08361598B2
公开(公告)日：2013-01-29
申请号：US12985456
申请日：2011-01-06
申请人： Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
发明人： Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
IPC分类号： B32B3/10 , B32B5/12 , H01L23/485 , H01L23/488
CPC分类号： H01L21/563 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/83 , H01L25/50 , H01L2224/0401 , H01L2224/05572 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/131 , H01L2224/14136 , H01L2224/26152 , H01L2224/29111 , H01L2224/2919 , H01L2224/73204 , H01L2224/831 , H01L2224/83385 , H01L2225/06513 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/0105 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/19041 , H01L2924/19043 , Y10S428/901 , Y10T29/49002 , Y10T29/49117 , Y10T29/4921 , Y10T29/49222 , Y10T428/24273 , Y10T428/24322 , Y10T428/24331 , Y10T428/24339 , Y10T428/24347 , Y10T428/24479 , Y10T428/24529 , Y10T428/24545 , Y10T428/24612 , H01L2924/00014 , H01L2924/01014 , H01L2924/01047 , H01L2924/01082 , H01L2224/13111 , H01L2924/0665 , H01L2224/05552 , H01L2924/00
摘要： An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.
摘要翻译： 一种电气结构和成型方法。 电结构包括第一衬底，第一介电层，底部填充层，第一焊料结构和第二衬底。 第一介电层形成在第一基板的顶表面上。 第一电介质层包括延伸穿过所述第一电介质层的顶表面和底表面的第一开口。 第一焊料结构形成在第一开口内以及在所述第一介电层的顶表面的一部分之上。 第二衬底形成在底部填充层上并与底部填充层接触。
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公开(公告)号：US20090256257A1
公开(公告)日：2009-10-15
申请号：US12102035
申请日：2008-04-14
申请人： Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , David L. Questad , Wolfgang Sauter
发明人： Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , David L. Questad , Wolfgang Sauter
IPC分类号： H01L23/52 , H01L23/488 , H01L21/44
CPC分类号： H01L23/53295 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/023 , H01L2224/0401 , H01L2224/05093 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01074 , H01L2924/01082 , H01L2924/14 , H01L2924/19041 , H01L2924/19043
摘要： A structure and a method for forming the same. The structure includes a first dielectric layer, an electrically conductive bond pad on the first dielectric layer, and a second dielectric layer on top of the first dielectric layer and the electrically conductive bond pad. The electrically conductive bond pad is sandwiched between the first and second dielectric layers. The second dielectric layer includes N separate final via openings such that a top surface of the electrically conductive bond pad is exposed to a surrounding ambient through each final via opening of the N separate final via openings. N is a positive integer greater than 1.
摘要翻译： 一种结构及其形成方法。 该结构包括第一电介质层，第一电介质层上的导电接合焊盘，以及在第一电介质层和导电接合焊盘顶部的第二电介质层。 导电接合焊盘夹在第一和第二电介质层之间。 第二电介质层包括N个独立的最终通路孔，使得导电接合焊盘的顶表面暴露于通过N个单独的最终通孔的每个最终通孔的周围环境。 N是大于1的正整数。
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9.发明申请公开(公告)号：US20090130599A1
公开(公告)日：2009-05-21
申请号：US11942753
申请日：2007-11-20
申请人： Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
发明人： Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
IPC分类号： G03F7/26
CPC分类号： H01L21/0272 , G03F7/095 , G03F7/168 , H01L24/11 , H01L24/12 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05556 , H01L2224/05568 , H01L2224/05655 , H01L2224/11334 , H01L2224/114 , H01L2224/11474 , H01L2224/1148 , H01L2224/116 , H01L2224/13021 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2924/01022 , H01L2924/01029 , H01L2924/01074 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/01082 , H01L2924/01047
摘要： An electrical structure and method of forming. The method comprises providing a substrate structure. A first layer comprising a first photosensitive material having a first polarity is formed over and in contact with the substrate structure. A second layer comprising photosensitive material having a second polarity is formed over and in contact with the first layer. The first polarity comprises an opposite polarity as the second polarity. Portions of the first and second layers are simultaneously exposed to a photo exposure light source. The portions of the first and second layers are developed such that structures are formed.
摘要翻译： 一种电气结构和成型方法。 该方法包括提供衬底结构。 包括具有第一极性的第一感光材料的第一层形成在衬底结构上并与衬底结构接触。 包含具有第二极性的感光材料的第二层形成在第一层之上并与第一层接触。 第一极性包括与第二极性相反的极性。 第一层和第二层的一部分同时暴露于曝光光源。 第一层和第二层的部分被显影以形成结构。
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公开(公告)号：US20070267746A1
公开(公告)日：2007-11-22
申请号：US11383595
申请日：2006-05-16
申请人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
CPC分类号： H01L24/10 , H01L23/13 , H01L23/481 , H01L23/49833 , H01L23/5385 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L2224/13 , H01L2224/13099 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H05K1/145 , H05K3/222 , H05K2201/10674 , Y10T436/171538 , Y10T436/172307 , H01L2924/00014 , H01L2924/00
摘要： An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.
摘要翻译： 一种电子装置和包装电子装置的方法。 该装置包括：第一基板，第二基板和具有第一侧和相对的第二侧的集成电路芯片，在第一侧上的第一组芯片焊盘和在集成的第二侧上的第二组芯片焊盘 电路芯片，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的对应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。
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