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    Substrate Processing System with Multiple Processing Devices Deployed in Shared Ambient Environment and Associated Methods
    12.
    发明申请
    Substrate Processing System with Multiple Processing Devices Deployed in Shared Ambient Environment and Associated Methods 审中-公开
    具有多个处理设备的基板处理系统部署在共享环境环境和相关方法中

    公开(公告)号：US20150079795A1

    公开(公告)日：2015-03-19

    申请号：US14548089

    申请日：2014-11-19

    Applicant: Lam Research Corporation

    Inventor： David J. Hemker ,  Lubab L. Sheet ,  Jeffrey Marks

    IPC: H01L21/3065 ,  H01L21/306 ,  H01L21/308

    CPC classification number: H01L21/3065 ,  C23C16/54 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/67051 ,  H01L21/67173 ,  H01L21/6776 ,  H01L21/68764 ,  H01L21/68771

    Abstract: A plurality of substrate processing devices are disposed in a separated manner within a shared ambient environment. A conveyance device is disposed within the shared ambient environment and is defined to move a substrate through and between each of the substrate processing devices in a continuous manner. Some substrate processing devices are defined to perform dry substrate processing operations in which an energized reactive environment is created in exposure to the substrate in an absence of liquid material. Some substrate processing devices are defined to perform wet substrate processing operations in which at least one material in a liquid state is applied to the substrate. In one embodiment, a complementary pair of dry and wet substrate processing devices are disposed in the shared ambient environment in a sequential manner relative to movement of the substrate by the conveyance device.

    Abstract translation: 多个基板处理装置以分开的方式设置在共享的环境环境中。 传送装置设置在共享的环境环境中，并被定义为以连续的方式移动基板通过每个基板处理装置之间和之间。 一些基板处理装置被定义为执行干基板处理操作，其中在没有液体材料的情况下在暴露于基板时产生通电的反应性环境。 一些基板处理装置被定义为执行湿基板处理操作，其中至少一种液态的材料被施加到基板。 在一个实施例中，互补的一对干式和湿式衬底处理装置相对于衬底由输送装置的移动以顺序的方式设置在共享的环境环境中。

    ATOMIC LAYER ETCHING OF GaN AND OTHER III-V MATERIALS
    16.
    发明申请
    ATOMIC LAYER ETCHING OF GaN AND OTHER III-V MATERIALS 审中-公开
    GaN和其他III-V材料的原子层蚀刻

    公开(公告)号：US20160358782A1

    公开(公告)日：2016-12-08

    申请号：US15173358

    申请日：2016-06-03

    Applicant: Lam Research Corporation

    Inventor： Wenbing Yang ,  Tomihito Ohba ,  Samantha Tan ,  Keren Jacobs Kanarik ,  Jeffrey Marks ,  Kazuo Nojiri

    IPC: H01L21/3065 ,  H01L29/205 ,  H01J37/32 ,  H01L29/66 ,  H01L21/67 ,  H01L29/20 ,  H01L29/778

    CPC classification number: H01L21/30621 ,  H01J37/321 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/67207 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

    Abstract: Provided herein are ALE methods of removing III-V materials such as gallium nitride (GaN) and related apparatus. In some embodiments, the methods involve exposing the III-V material to a chlorine-containing plasma without biasing the substrate to form a modified III-V surface layer; and applying a bias voltage to the substrate while exposing the modified III-V surface layer to a plasma to thereby remove the modified III-V surface layer. The disclosed methods are suitable for a wide range of applications, including etching processes for trenches and holes, fabrication of HEMTs, fabrication of LEDs, and improved selectivity in etching processes.

    Abstract translation: 本文提供了除去III-V材料如氮化镓（GaN）和相关装置的ALE方法。 在一些实施方案中，所述方法包括将III-V材料暴露于含氯等离子体中，而不偏压衬底以形成修饰的III-V表面层; 以及在将所述修饰的III-V表面层暴露于等离子体的同时向所述衬底施加偏置电压，从而去除所述修饰的III-V表面层。 所公开的方法适用于广泛的应用，包括用于沟槽和孔的蚀刻工艺，HEMT的制造，LED的制造以及蚀刻工艺中的改进的选择性。

    CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
    18.
    发明授权
    CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications 有权
    CVD金属/半导体OHMIC接触用于大批量制造应用

    公开(公告)号：US09153486B2

    公开(公告)日：2015-10-06

    申请号：US13862048

    申请日：2013-04-12

    Applicant: Lam Research Corporation

    Inventor： Reza Arghavani ,  Jeffrey Marks ,  Benjamin A. Bonner

    IPC: H01L21/768

    CPC classification number: H01L21/7688 ,  H01L21/285 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/485 ,  H01L29/0895 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An apparatus and method for manufacturing an interconnect structure to provide ohmic contact in a semiconductor device is provided. The method includes providing a semiconductor device, such as a transistor, comprising a substrate, a gate dielectric, a gate electrode, and source and drain regions in the substrate. An ultra-thin interfacial dielectric is deposited by chemical vapor deposition (CVD) over the source and drain regions, where the interfacial dielectric can have a thickness between about 3 Å and about 20 Å. The ultra-thin interfacial dielectric is configured to unpin the metal Fermi level from the source and drain regions. Other steps such as the deposition of a metal by CVD and the cleaning of the substrate surface can be performed in an integrated process tool without a vacuum break. The method further includes forming one or more vias through a pre-metal dielectric over the source and drain regions of the substrate.

    Abstract translation: 提供一种用于制造在半导体器件中提供欧姆接触的互连结构的装置和方法。 该方法包括在衬底中提供诸如晶体管的半导体器件，其包括衬底，栅极电介质，栅极电极以及源极和漏极区域。 通过在源极和漏极区域上的化学气相沉积（CVD）沉积超薄界面电介质，其中界面电介质可以具有在约和之间的厚度。 超薄界面电介质被配置为从源极和漏极区域去除金属费米能级。 其他步骤，例如通过CVD沉积金属和清洁基板表面可以在没有真空断裂的一体化工艺工具中进行。 该方法还包括在衬底的源极和漏极区域上形成通过前金属电介质的一个或多个通孔。

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