公开(公告)号：US08547774B2

公开(公告)日：2013-10-01

申请号：US12697150

申请日：2010-01-29

申请人： Richard S. Roy ,  Dipak Kumar Sikdar

发明人： Richard S. Roy ,  Dipak Kumar Sikdar

IPC分类号： G11C8/00 ,  G11C8/16

CPC分类号： G11C7/00 ,  G11C7/1075 ,  G11C11/413

摘要： A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.

公开(公告)号：US20110191548A1

公开(公告)日：2011-08-04

申请号：US12697141

申请日：2010-01-29

申请人： Michael J. Miller ,  Richard S. Roy

发明人： Michael J. Miller ,  Richard S. Roy

IPC分类号： G06F12/08 ,  G06F13/12

CPC分类号： G06F13/1647

摘要： A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency.

摘要翻译： 一种存储装置，包括在第一多个串行链路上接收指令和输入数据的输入接口。 指令和输入数据在存储器件上反序列化，并被提供给存储器控制器。 存储器控制器响应于接收的指令启动对存储器内核的访问。 存储器核心包括以循环和重叠的方式访问的多个存储器分区。 这允许每个存储器分区以比串行链路更低的频率工作，同时正确地维护接收到的指令。 以同步方式执行对存储设备的访问，其中每个访问呈现已知的固定等待时间。

公开(公告)号：US06466504B1

公开(公告)日：2002-10-15

申请号：US09590619

申请日：2000-06-08

申请人： Richard S. Roy

发明人： Richard S. Roy

IPC分类号： G11C700

CPC分类号： G11C11/419 ,  G11C7/20 ,  G11C2207/002

摘要： A circuit for selectively erasing a semiconductor memory instance on a per I/O basis. The circuit is provided as a tilable architectural element in a memory compiler for the semiconductor memory instance. A plurality of pass gates are disposed between global wordlines provided by the row decoder of the memory array and local wordlines that select memory bit cells in a particular I/O. One or more memory clear signals are used to decouple the local wordlines from the global wordlines and to connect them to a high voltage node, VDD. The I/O is cleared by placing a predetermined logic state (typically 0) on the bitline nodes of the I/O and selectively coupling the local wordlines to the VDD node.

摘要翻译： 一种用于以每I / O为基础选择性地擦除半导体存储器实例的电路。 该电路作为半导体存储器实例的存储器编译器中的可倾斜架构元件提供。 在由存储器阵列的行解码器提供的全局字线和选择特定I / O中的存储器位单元的本地字线之间设置多个通道。 一个或多个存储器清除信号用于将本地字线与全局字线分离并将其连接到高电压节点VDD。 通过在I / O的位线节点上放置预定的逻辑状态（通常为0）来清除I / O，并选择性地将本地字线耦合到VDD节点。

公开(公告)号：US06249471B1

公开(公告)日：2001-06-19

申请号：US09605221

申请日：2000-06-28

申请人： Richard S. Roy

发明人： Richard S. Roy

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106

摘要： A full signal swing differential output path circuit for rapidly transferring a latched data value on a pair of complementary global data nodes (QT and QB) to a single-ended output of a compilable memory instance. At least one tri-statable sense amplifier is disposed between the complementary global data nodes which operates to sense a small differential voltage between a pair of complementary bitlines disposed in a bank of memory storage cells during an access operation associated therewith. A pair of precharge pull up devices are provided for precharging the complementary global data nodes QT and QB to a predetermined voltage, e.g., VDD. In a preferred embodiment, the precharge pull up devices preferably comprise P-channel MOS (PMOS) devices and are actuatable by an active low precharge signal. A first output of the sense amp is coupled to one of the complementary global data nodes (QB) and the complementary output (i.e., second output) of the sense amp is coupled to the other complementary global data node (QT) to quickly drive either QT or QB to ground as soon as the bitline polarity is sensed by the sense amp. The output structure then quickly takes the full differential value between QT and QB and drives the single-ended output of the memory instance rapidly to either VDD or ground. A CMOS pass gate actuatable by an output enable signal is disposed on the QB data path, wherein the pass gate operates to drive an output pull up device coupled to the output of the memory instance. A NOR gate is coupled to the QT data path and an inverted signal derived from the output enable signal, wherein the NOR gate operates to drive a output pull down device coupled to the single-ended output of the memory instance.

摘要翻译： 全信号摆幅差分输出路径电路，用于将一对互补的全局数据节点（QT和QB）上的锁存数据值快速传输到可编译存储器实例的单端输出。 在互补的全局数据节点之间设置至少一个三态读出放大器，该互补全局数据节点用于在与其相关联的访问操作期间感测布置在一组存储器存储单元中的一对互补位线之间的小的差分电压。 提供一对预充电上拉装置用于将互补的全局数据节点QT和QB预充电到预定电压，例如VDD。 在优选实施例中，预充电上拉器件优选地包括P沟道MOS（PMOS）器件，并且可由有源低预充电信号驱动。 感测放大器的第一输出耦合到互补全局数据节点（QB）之一，并且感测放大器的互补输出（即，第二输出）耦合到另一个互补全局数据节点（QT），以快速驱动 一旦感测放大器检测到位线极性，QT或QB将接地。 然后，输出结构将快速获取QT和QB之间的全差分值，并将存储器实例的单端输出快速驱动为VDD或接地。 可通过输出使能信号驱动的CMOS通过栅极设置在QB数据通路上，其中，通过栅极操作以驱动耦合到存储器实例的输出的输出上拉器件。 NOR门耦合到QT数据路径和从输出使能信号导出的反相信号，其中或非门操作以驱动耦合到存储器实例的单端输出的输出下拉器件。

公开(公告)号：US08539196B2

公开(公告)日：2013-09-17

申请号：US12697132

申请日：2010-01-29

申请人： Richard S. Roy

发明人： Richard S. Roy

IPC分类号： G06F12/00

CPC分类号： G11C11/408 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4096 ,  G11C11/4097

摘要： A multi-bank memory system includes one or more levels of logical memory hierarchy to increase the available random cyclic transaction rate of the memory system. The memory system includes a plurality of multi-bank partitions, each having a corresponding partition interface. Each partition interface accesses the corresponding multi-bank partition at a first frequency. A global interface may access the partition interfaces at a second frequency, which is equal to the first frequency times the number of partition interfaces. Alternately, a plurality of cluster interfaces may access corresponding groups of the partition interfaces, wherein each cluster interface accesses the corresponding group of partition interfaces at a second frequency that is faster than the first frequency. A global interface accesses the cluster interfaces at a third frequency that is greater than the second frequency.

摘要翻译： 多存储存储器系统包括一个或多个逻辑存储器层级以增加存储器系统的可用随机循环事务速率。 存储器系统包括多个多块分区，每个分区具有对应的分区接口。 每个分区接口以第一个频率访问相应的多存储体分区。 全局接口可以以等于第一个频率乘以分区接口数的第二个频率访问分区接口。 或者，多个群集接口可以访问分区接口的相应组，其中每个群集接口以比第一频率快的第二频率访问对应的分组接口组。 全局接口以大于第二个频率的第三个频率访问集群接口。

公开(公告)号：US20120140581A1

公开(公告)日：2012-06-07

申请号：US13369253

申请日：2012-02-08

申请人： Richard S. Roy

发明人： Richard S. Roy

IPC分类号： G11C7/00

CPC分类号： G11C7/1015 ,  G11C11/406 ,  G11C11/40618 ,  G11C2207/229

摘要： A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.

摘要翻译： 一种通过执行不完整的写入操作来减少存储器单元的存储器周期时间的存储器系统。 在不完全写入操作期间，存储单元的存储节点上的电压未达到全电源电压。 随后通过一个或多个附加访问完成不完整的写入操作，其中存储节点上的电压被拉至完全电源电压。 可以通过以下方式完成不完整的写入操作：随后在空闲周期期间将相同的数据写入存储器单元; 随后将数据写入到与存储器单元相同的行中的其他存储单元; 随后从包括存储器单元的行读取数据; 或者在空闲周期期间刷新包含存储单元的行。 可能会迫使一个或多个空闲周期及时完成不完整的写入操作。

公开(公告)号：US20110188335A1

公开(公告)日：2011-08-04

申请号：US12697150

申请日：2010-01-29

申请人： Richard S. Roy ,  Dipak Kumar Sikdar

发明人： Richard S. Roy ,  Dipak Kumar Sikdar

IPC分类号： G11C8/00 ,  G11C8/16

CPC分类号： G11C7/00 ,  G11C7/1075 ,  G11C11/413

摘要： A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.

摘要翻译： 存储器系统包括多个（N）个存储体和多个（M）端口，其中N大于或等于M.存储器组中的每一个耦合到每个端口。 在每个端口上同时发送访问请求。 然而，每个同时访问请求指定了不同的存储体。 每个存储器监视端口上的访问请求，并确定任何访问请求是否指定存储体。 在确定访问请求指定存储体时，存储体执行对单端口存储单元阵列的访问。 在多个存储体中执行同时访问，提供等于一个存储体的带宽乘以端口数的带宽。 可以提供额外的层次级别，这允许以最小的面积开销进一步增加同时访问的端口的数量。

公开(公告)号：US06480978B1

公开(公告)日：2002-11-12

申请号：US09260459

申请日：1999-03-01

申请人： Richard S. Roy ,  Charles A. Miller

发明人： Richard S. Roy ,  Charles A. Miller

IPC分类号： G01R3128

CPC分类号： G11C29/56 ,  G01R31/31905 ,  G01R31/3193 ,  H01L2224/16225 ,  H01L2924/19107

摘要： What is disclosed is a system for testing a plurality of integrated circuit devices under test (DUTs), that includes a tester having at least one set of tester input/output (I/O) lines, the tester providing data values for testing a single DUT on the set of tester I/O lines, and circuitry coupled to the set of tester I/O lines to receive the data values from the tester and to provide error values to the tester, the circuitry forwards the data values to each of the plurality of DUTs, the circuitry performs a first comparison of the values of two locations having corresponding addresses in different DUTs after reading from the locations, and in response generates the error values indicative of the first comparison. The circuitry may further perform a second comparison of the values of two different locations in the same DUT to generate further error values indicative of the second comparison.

摘要翻译： 所公开的是用于测试被测试的多个集成电路器件（DUT）的系统，其包括具有至少一组测试器输入/输出（I / O）线的测试器，该测试器提供用于测试单个 测试仪I / O线上的DUT，以及耦合到一组测试仪I / O线的电路，以从测试器接收数据值，并向测试者提供错误值，电路将数据值转发到每个 多个DUT，电路在从该位置读取之后对不同DUT中具有相应地址的两个位置的值执行第一比较，并且响应于产生指示第一比较的误差值。 该电路还可以执行相同DUT中的两个不同位置的值的第二比较，以产生指示第二比较的另外的误差值。

公开(公告)号：US06392957B1

公开(公告)日：2002-05-21

申请号：US09728377

申请日：2000-11-28

申请人： Alexander Shubat ,  Adam Kablanian ,  Jaroslav Raszka ,  Richard S. Roy

发明人： Alexander Shubat ,  Adam Kablanian ,  Jaroslav Raszka ,  Richard S. Roy

IPC分类号： G11C722

CPC分类号： G11C7/227 ,  G11C7/22 ,  G11C2207/104

摘要： A self-timed write control memory device minimizes the memory cycle time for the cells of the array. The self-timed write control memory device preferably comprises an X-decoder, a word-line driver, a memory cell array, control logic, pre-charge circuits, sense amplifiers, a reference decoder, and a reference word-line driver. The memory device preferably further includes a first reference cell, a second reference cell or logic, a first reference column, a second reference column and a reference sense amplifier. The first reference cell is preferably used for detection of read cycle completion and the second reference cell or logic is used for detection of write cycle completion. The output of the first reference cell and second reference cell are preferably coupled to inputs of a unique reference sense amplifier. The sense amplifier includes special circuitry that uses either the output of the first reference cell or the second reference cell to generate the self-timed clock and there by minimizes the memory cycle time. The second reference cell may be any one of a conventional memory cell or write reference logic.

摘要翻译： 自定时的写入控制存储器件最小化阵列的单元的存储器周期时间。 自定时写控制存储器件优选地包括X解码器，字线驱动器，存储单元阵列，控制逻辑，预充电电路，读出放大器，参考解码器和参考字线驱动器。 存储器件优选地还包括第一参考单元，第二参考单元或逻辑，第一参考列，第二参考列和参考读出放大器。 第一参考单元优选地用于检测读周期完成，并且第二参考单元或逻辑用于检测写周期完成。 第一参考单元和第二参考单元的输出优选地耦合到唯一参考读出放大器的输入。 读出放大器包括专用电路，其使用第一参考单元或第二参考单元的输出来产生自定时钟，并且通过使存储器周期时间最小化。 第二参考单元可以是常规存储单元或写入参考逻辑中的任何一个。

公开(公告)号：US06330164B1

公开(公告)日：2001-12-11

申请号：US09114589

申请日：1998-07-13

申请人： Igor Y. Khandros ,  David V. Pedersen ,  Benjamin N. Eldridge ,  Richard S. Roy ,  Gaetan Mathieu

发明人： Igor Y. Khandros ,  David V. Pedersen ,  Benjamin N. Eldridge ,  Richard S. Roy ,  Gaetan Mathieu

IPC分类号： H05K702

CPC分类号： H05K7/1069 ,  B23K20/004 ,  B23K2101/40 ,  C25D7/12 ,  G01R1/0483 ,  G01R31/2889 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4015 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2224/29099 ,  H01L2924/00

摘要： The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry. One particularly preferred mode of connection is by incorporating resilient, free-standing contact structures on the same semiconductor device, with the structures standing farther away from the semiconductor and the capacitor. Other useful connectors include providing similar resilient, free-standing contact structures on the other device, then positioning the semiconductor over the resilient contacts and securing the two devices together. A socket with such resilient structures is particularly useful for this application. In an alternative preferred embodiment, the capacitor and resilient contacts all are incorporated in the second device, such as a socket. In one aspect of the invention, the ancillary electrical component may include a travel stop structure which defines a minimum separation between the semiconductor and a substrate such as a printed circuit board.

摘要翻译： 本发明提供了非常接近半导体器件的辅助电气部件，优选地直接安装在半导体器件上。 在一个优选实施例中，辅助电气部件是电容器。 在优选实施例中，端子设置在半导体器件上，使得电容器可以通过焊接或与导电环氧树脂直接电连接到端子。 在电源回路端子之间连接电容器可提供卓越的噪声和瞬态抑制。 电容器和有源电路之间的非常短的路径提供极低的电感，允许使用相对较小的电容器。 然后，半导体器件连接到诸如PC板的电子设备，用于进一步连接到其它电路。 一个特别优选的连接方式是通过在相同的半导体器件上并入弹性，独立的接触结构，其结构远离半导体和电容器。 其他有用的连接器包括在另一装置上提供类似的弹性，独立的接触结构，然后将半导体定位在弹性触点上并将两个装置固定在一起。 具有这种弹性结构的插座对于该应用特别有用。 在替代的优选实施例中，电容器和弹性触点都被并入第二装置，例如插座。 在本发明的一个方面，辅助电气部件可以包括限定半导体和诸如印刷电路板的基板之间的最小间隔的行进止动结构。