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    Packing density for flash memories
    11.
    发明授权
    Packing density for flash memories 失效
    闪存的包装密度

    公开(公告)号：US5622881A

    公开(公告)日：1997-04-22

    申请号：US319393

    申请日：1994-10-06

    申请人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    发明人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

    摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

    摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

    Self-aligned lateral bipolar transistors
    12.
    发明授权
    Self-aligned lateral bipolar transistors 失效
    自对准侧向双极晶体管

    公开(公告)号：US4641170A

    公开(公告)日：1987-02-03

    申请号：US762669

    申请日：1985-08-05

    申请人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Joseph F. Shepard

    发明人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Joseph F. Shepard

    IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/72

    CPC分类号： H01L29/6625 ,  H01L29/66272 ,  H01L29/66606

    摘要： An integrated circuit structure which includes small area lateral bipolar and method for making the same is described. A semiconductor body, such as a monocrystalline silicon wafer, having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction base region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers are in electrical contact with an edge of each of the vertical conductive layers and separated from the surface regions by a first electrical insulating layer. A second insulating layer covers the conformal conductive layers. The horizontal conductive layer is patterned so as to have electrically separated conductive lines from one another. A third electrical insulating layer is located over the patterned horizontal conductive layers. An electrical ohmic contact is made to each of the horizontal conductive layers through an opening in the third electrical insulating layer which effectively makes electrical contacts to the emitter and collector regions through the patterned horizontal conductive layers and the vertical conductive layers. An electrical ohmic contact is made to the centrally located base region which contact is separated from the vertical conductive layers by the second insulating layer.

    摘要翻译： 描述了包括小面积横向双极的集成电路结构及其制造方法。 提供了半导体本体，例如单晶硅晶片，其表面区域通过介电隔离图案与其它这样的区域隔离。 至少两个窄宽度PN结区域位于至少一个表面区域内。 每个PN结的宽度尺寸基本上是其电接触点。 基本上垂直的保形导电层电阻接触每个PN结区域。 PN结区域是用于横向双极晶体管的发射极和集电极区域。 具有相反电导率的基极PN结基区位于发射极和集电极结之间并且与发射极和集电极结邻接。 基本上水平的导电层与每个垂直导电层的边缘电接触，并通过第一电绝缘层与表面区域分离。 第二绝缘层覆盖保形导电层。 将水平导电层图案化成具有彼此分离的导电线。 第三电绝缘层位于图案化的水平导电层上。 通过第三电绝缘层中的开口对每个水平导电层进行电欧姆接触，其有效地通过图案化的水平导电层和垂直导电层与发射极和集电极区域电接触。 对中心位置的基极区域进行电欧姆接触，该接触部分通过第二绝缘层与垂直导电层分离。

    Method of making a DRAM cell with trench capacitor
    13.
    发明授权
    Method of making a DRAM cell with trench capacitor 失效
    制造具有沟槽电容器的DRAM单元的方法

    公开(公告)号：US5395786A

    公开(公告)日：1995-03-07

    申请号：US269852

    申请日：1994-06-30

    申请人： Louis L. Hsu ,  Sieki Ogura ,  Joseph F. Shepard

    发明人： Louis L. Hsu ,  Sieki Ogura ,  Joseph F. Shepard

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10861

    摘要： A DRAM cell of the trench capacitor type is formed by a simplified process that reduces cost and increases process latitude by forming the trench collar in a single step of expanding a shallow trench horizontally and conformally coating the collar; etching the trench to its final depth and implanting the bottom heavily and doping the walls lightly; recessing the poly liner in a non-critical step that exposes a contact area between the top of the poly and the adjacent transistor electrode.

    摘要翻译： 沟槽电容器类型的DRAM单元通过简化的工艺形成，该工艺通过在使水平并且适形地涂覆套环的单个步骤中形成沟槽套圈来降低成本并增加工艺的纬度; 将沟槽蚀刻到其最终深度并且重要地注入底部并轻轻掺杂壁; 在暴露多晶硅和相邻晶体管电极的顶部之间的接触面积的非关键步骤中使多层衬垫凹陷。

    Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding
    14.
    发明授权
    Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding 失效
    半导体器件和晶片结构通过晶片接合具有平面埋入互连

    公开(公告)号：US5382832A

    公开(公告)日：1995-01-17

    申请号：US131344

    申请日：1993-10-04

    申请人： Taqi N. Buti ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Joseph F. Shepard

    发明人： Taqi N. Buti ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Joseph F. Shepard

    IPC分类号： H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L23/48 ,  H01L27/01

    CPC分类号： H01L25/50 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L2924/0002 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S438/977

    摘要： A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate having an oxide layer thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

    摘要翻译： 公开了一种适于在其上形成半导体器件的晶片结构，并且具有用于根据预定互连图案互连所需半导体器件的掩埋互连结构及其制造方法。 晶片结构包括具有适于形成期望的半导体器件的第一厚度的初级衬底。 主衬底还包括：a）根据预定互连图案形成在初级衬底的底表面上的第二厚度的导电互连衬垫，b）形成在第一衬底的底表面上的第三厚度的第一隔离衬垫 导电互连焊盘，以及c）形成在与主基板相对的互连焊盘的表面上的第四厚度的互连焊盘盖，其中互连焊盘帽包括适于晶片接合的材料，并且其中第二厚度 厚度和第四厚度等于第三厚度。 该结构还包括其上结合有互连衬垫帽和主晶片的第一隔离垫的氧化物层的二次衬底。

    Method of making thin film transistor with a self-aligned bottom gate using diffusion from a dopant source layer
    15.
    发明授权
    Method of making thin film transistor with a self-aligned bottom gate using diffusion from a dopant source layer 失效
    利用来自掺杂剂源层的扩散制造具有自对准底栅的薄膜晶体管的方法

    公开(公告)号：US5573964A

    公开(公告)日：1996-11-12

    申请号：US559809

    申请日：1995-11-17

    申请人： Louis L. Hsu ,  Mary J. Saccamango ,  Joseph F. Shepard

    发明人： Louis L. Hsu ,  Mary J. Saccamango ,  Joseph F. Shepard

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/84

    CPC分类号： H01L29/66765 ,  H01L29/42384 ,  H01L29/78621 ,  H01L29/4908

    摘要： A simple method of making a thin film transistor (TFT) on a substrate with an insulating surface layer is disclosed. A layer of dopant source layer is deposited on the insulating layer, followed by defining a gate stack consisting of a gate polysilicon, gate insulator and a protective polysilicon using the dopant source layer as an etch stop. Sidewall spacers are formed in contact with the gate stack. A TFT body polysilicon is deposited and patterned, forming thereby the source and drain regions in a self-aligned manner. By heating, the dopants from the dopant source layer are driven into the source/drain and to part of the off-set regions of the body polysilicon layer while simultaneously also doping the gate polysilicon.

    摘要翻译： 公开了一种在具有绝缘表面层的衬底上制造薄膜晶体管（TFT）的简单方法。 掺杂剂源层的一层沉积在绝缘层上，随后使用掺杂剂源层作为蚀刻停止层，由栅极多晶硅，栅极绝缘体和保护性多晶硅构成的栅极叠层。 侧壁间隔件形成为与栅极堆叠接触。 沉积并图案化TFT体多晶硅，从而以自对准的方式形成源区和漏区。 通过加热，来自掺杂剂源层的掺杂剂被驱动到源极/漏极和体内多晶硅层的偏移区域的一部分，同时也掺杂栅极多晶硅。

    Vertical dual gate thin film transistor with self-aligned gates / offset drain
    16.
    发明授权
    Vertical dual gate thin film transistor with self-aligned gates / offset drain 失效
    具有自对准栅极/漏极漏极的垂直双栅极薄膜晶体管

    公开(公告)号：US5574294A

    公开(公告)日：1996-11-12

    申请号：US576103

    申请日：1995-12-22

    申请人： Joseph F. Shepard

    发明人： Joseph F. Shepard

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/76 ,  H01L21/265

    CPC分类号： H01L29/6675 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78642 ,  H01L29/78648

    摘要： A process for making a dual gated thin film transistor (TFT), having a sidewall channel and self-aligned gates and off-set drain is disclosed. A substrate having a top surface with insulating regions is provided. A bilayer having a polysilicon bottom layer and an insulating top layer, is patterned to form the bottom electrode of the TFT with an insulating layer over it. A first gate insulator is formed in contact with sides of the bottom electrode. A layer of second polysilicon having two end source and drain regions and a middle channel region is formed with the channel region being vertical along the side of the bottom electrode and overlying insulator layer and in contact with the first gate insulator. A second gate insulator is formed on the second polysilicon. A contact opening is etched in the insulating layers overlying the bottom electrode, in a region away from the second polysilicon to expose surface of part of the bottom electrode. A third polysilicon layer is deposited and patterned to have a horizontal region overlapping the contact opening to make contact to the bottom electrode, and to have sidewall electrode regions in contact with the second gate insulator and superadjacent to the channel region act as the top electrode of the TFT. The sidewall spacer electrode regions are connected to the horizontal regions of the third polysilicon. Thus the top and bottom electrode are also electrically connected together. The source and drain regions are doped selectively. By choice of implant conditions, the off-set region having a desired dopant concentration different from the device layer concentration, can be formed at the drain side of the dual gated TFT.

    摘要翻译： 公开了一种制造具有侧壁通道和自对准栅极和偏置漏极的双门控薄膜晶体管（TFT）的工艺。 提供了具有绝缘区域的顶面的基板。 将具有多晶硅底层和绝缘顶层的双层图案化以形成TFT上的绝缘层的TFT的底部电极。 第一栅极绝缘体形成为与底部电极的侧面接触。 形成具有两个端部源极和漏极区域以及中间沟道区域的第二多晶硅层，其中沟道区域沿着底部电极和上部绝缘体层的侧面是垂直的并且与第一栅极绝缘体接触。 在第二多晶硅上形成第二栅极绝缘体。 在覆盖底部电极的绝缘层中，在远离第二多晶硅的区域中蚀刻接触开口以暴露底部电极的一部分的表面。 第三多晶硅层被沉积和图案化以具有与接触开口重叠的水平区域以与底部电极接触，并且具有与第二栅极绝缘体接触并且与沟道区域相邻的侧壁电极区域用作顶部电极 TFT。 侧壁间隔电极区域连接到第三多晶硅的水平区域。 因此，顶部和底部电极也电连接在一起。 源区和漏区被选择性掺杂。 通过选择注入条件，可以在双门控TFT的漏极侧形成具有不同于器件层浓度的期望掺杂剂浓度的偏移区域。

    Formation of bit lines for ram device
    20.
    发明授权
    Formation of bit lines for ram device 失效
    形成柱塞装置的位线

    公开(公告)号：US4403394A

    公开(公告)日：1983-09-13

    申请号：US217371

    申请日：1980-12-17

    申请人： Joseph F. Shepard ,  Paul J. Tsang

    发明人： Joseph F. Shepard ,  Paul J. Tsang

    IPC分类号： H01L27/10 ,  H01L21/28 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/532 ,  H01L27/108 ,  H01L29/78 ,  H01L21/22

    CPC分类号： H01L21/76889 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S438/98

    摘要： A conductor bit line for a dynamic random access memory (RAM) structure is formed of a material selected from the group consisting of polycrystalline silicon and a metal silicide, polycrystalline silicon and a conductive metal, and polycrystalline silicon, a metal silicide, and a conductive metal with the polycrystalline silicon contacting at least a portion of the drain region of the field effect transistor of each of a plurality of cells of the RAM structure via a self-aligned contact. When the selected material is polycrystalline silicon and a metal silicide, the conductor bit line is continuous. When the selected material is polycrystalline silicon and a conductive metal or polycrystalline silicon, a metal silicide, and a conductive metal, the polycrystalline silicon contacts with each of the drain regions while the conductive metal connects the polycrystalline silicon overlying adjacent drain regions when the selected material is polycrystalline silicon and a conductive metal and connects the metal silicide on the polycrystalline silicon overlying adjacent drain regions when the selected material is polycrystalline silicon, a metal silicide, and a conductive metal.

    摘要翻译： 用于动态随机存取存储器（RAM）结构的导体位线由选自多晶硅和金属硅化物，多晶硅和导电金属的组中的材料形成，多晶硅，金属硅化物和导电 金属与多晶硅经由自对准接触接触RAM结构的多个单元中的每一个的场效应晶体管的漏极区域的至少一部分。 当所选择的材料是多晶硅和金属硅化物时，导体位线是连续的。 当所选择的材料是多晶硅和导电金属或多晶硅，金属硅化物和导电金属时，多晶硅与每个漏极区接触，而当所选材料的导电金属连接覆盖相邻漏极区的多晶硅时 是多晶硅和导电金属，并且当所选择的材料是多晶硅，金属硅化物和导电金属时，将覆盖在相邻漏极区域上的多晶硅上的金属硅化物连接。