公开(公告)号：US20160359488A1

公开(公告)日：2016-12-08

申请号：US15091588

申请日：2016-04-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Sheng-Feng Lee

IPC: H03L1/00 ,  H04L7/06 ,  H03L7/00 ,  H04L7/00

CPC classification number: H03L1/00 ,  G01R31/31709 ,  H03L7/00 ,  H04L7/0087 ,  H04L7/065

Abstract: A jitter control circuit within a chip comprises an adaptive PDN, a current generator and a jitter generator. The adaptive PDN is capable of being controlled/modulated to provide difference impedances. The current generator is coupled to the adaptive PDN, and is arranged for receiving a supply voltage provided by the adaptive PDN and generating currents with different patterns. The jitter generator is coupled to the adaptive PDN, and is arranged for generating a plurality of jitters corresponding to the currents with different patterns, respectively, according to the supply voltage provided by the adaptive PDN.

Abstract translation: 芯片内的抖动控制电路包括自适应PDN，电流发生器和抖动发生器。 自适应PDN能够被控制/调制以提供差分阻抗。 电流发生器耦合到自适应PDN，并且被布置为用于接收由自适应PDN提供的电源电压并且生成具有不同模式的电流。 抖动发生器耦合到自适应PDN，并且被配置为根据由自适应PDN提供的电源电压分别产生对应于具有不同模式的电流的多个抖动。

公开(公告)号：US20170222647A1

公开(公告)日：2017-08-03

申请号：US15247903

申请日：2016-08-25

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Chia-Yu Chan ,  Bo-Wei Hsieh

IPC: H03K19/00 ,  G06F3/06 ,  G11C11/4074

CPC classification number: H03K19/0005 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0683 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4074 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.

公开(公告)号：US20170221544A1

公开(公告)日：2017-08-03

申请号：US15247870

申请日：2016-08-25

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Chia-Yu Chan ,  Bo-Wei Hsieh

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C5/066 ,  G11C7/1084 ,  G11C7/225 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.

公开(公告)号：US09473142B2

公开(公告)日：2016-10-18

申请号：US14830755

申请日：2015-08-20

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  An-Siou Li

IPC: G11C7/10 ,  H03K19/0175

CPC classification number: H03K19/017509 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018507

Abstract: A method for performing signal driving control in an electronic device and an associated apparatus are provided. The method includes: generating a first driving control signal and a second driving control signal according to a data signal, wherein the second driving control signal transits in response to a transition of the data signal, and the first driving control signal includes a pulse corresponding to the transition of the data signal; and utilizing a first switching unit to control a first signal path between a first voltage level and an output terminal of an output stage according to the first driving control signal, and utilizing a second switching unit to control a second signal path between the first voltage level and the output terminal according to the second driving control signal, wherein a first impedance of the first signal path is less than a second impedance of the second signal path.

Abstract translation: 提供了一种在电子设备和相关设备中执行信号驱动控制的方法。 该方法包括：根据数据信号产生第一驱动控制信号和第二驱动控制信号，其中第二驱动控制信号响应于数据信号的转变而转换，并且第一驱动控制信号包括对应于 数据信号的转换; 以及利用第一开关单元根据第一驱动控制信号来控制输出级的第一电压电平和输出端之间的第一信号路径，并且利用第二开关单元来控制第一电压电平 以及根据第二驱动控制信号的输出端子，其中第一信号路径的第一阻抗小于第二信号路径的第二阻抗。

公开(公告)号：US20160173082A1

公开(公告)日：2016-06-16

申请号：US14830738

申请日：2015-08-20

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Sheng-Feng Lee

IPC: H03K17/56

CPC classification number: H03K17/56 ,  G06F1/26

Abstract: A method and apparatus for performing impedance profile control of a power delivery network (PDN) in an electronic device are provided. The method includes the steps of: utilizing a capacitive component and a resistive component that are coupled in series as an output stage of the PDN, wherein the capacitive component includes one terminal coupled to a first voltage level of the PDN and further includes another terminal, and the resistive component includes a first terminal coupled to the other terminal of the capacitive component and further includes a second terminal coupled to a second voltage level of the PDN; and inputting a control signal into a third terminal of the resistive component, to control an impedance profile of the output stage of the PDN, wherein in a predetermined state of the control signal, the control signal is a time variant signal. The control signal may be digital or analog.

Abstract translation: 提供了一种用于在电子设备中执行电力输送网络（PDN）的阻抗曲线控制的方法和装置。 该方法包括以下步骤：利用串联耦合作为PDN的输出级的电容部件和电阻部件，其中电容部件包括耦合到PDN的第一电压电平的一个端子，并且还包括另一个端子， 并且所述电阻部件包括耦合到所述电容部件的另一端的第一端子，并且还包括耦合到所述PDN的第二电压电平的第二端子; 以及将控制信号输入到所述电阻部件的第三端子中，以控制所述PDN的输出级的阻抗曲线，其中在所述控制信号的预定状态下，所述控制信号是时变信号。 控制信号可以是数字或模拟的。

公开(公告)号：US20150255129A1

公开(公告)日：2015-09-10

申请号：US14535299

申请日：2014-11-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G11C7/10

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0994 ,  H03L2207/50

Abstract: A method for performing memory interface control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of a memory interface circuit of the electronic device, and the memory interface circuit is arranged for controlling a random access memory (RAM) of the electronic device; applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the memory interface circuit is calibrated with aid of the at least one phase shift.

Abstract translation: 提供了一种用于执行电子设备和相关设备的存储器接口控制的方法，其中该方法包括以下步骤：当检测到数据信号和时钟信号之间的相位差达到预定值时，控制时钟 信号从第一频率切换到第二频率，其中时钟信号和数据信号都是电子设备的存储器接口电路的信号，并且存储器接口电路被布置用于控制随机存取存储器（RAM） 的电子设备; 对数据信号施加至少一个相移，直到满足条件; 以及控制所述时钟信号从所述第二频率切换到所述第一频率; 其中所述存储器接口电路借助于所述至少一个相移被校准。

公开(公告)号：US20150170719A1

公开(公告)日：2015-06-18

申请号：US14294094

申请日：2014-06-02

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G11C7/10 ,  G11C29/54

CPC classification number: G11C7/109 ,  G06F13/1689 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/028 ,  H03K19/018557 ,  H04L25/0278 ,  H04L25/0298

Abstract: A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.

Abstract translation: 提供了一种用于在电子设备，相关设备和相关联的存储器控​​制器中执行存储器接口校准的方法，其中所述方法包括：控制所述存储器控制器的数字终端上的信号以在多个级别之间切换，其中， 数字终端耦合到电子设备的存储器; 并且基于从所述信号的检测获得的至少一个检测结果，校准所述信号的逻辑状态以对应于所述多个电平的电平。 更具体地，存储器控制器可以包括用于将存储器控制器耦合到存储器的多个命令终端，多个数据终端和至少一个时钟终端。 例如，数字终端可以是命令终端或数据终端。

公开(公告)号：US20150074346A1

公开(公告)日：2015-03-12

申请号：US14324228

申请日：2014-07-06

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Pin Chen

IPC: G11C7/10 ,  G11C8/12

CPC classification number: G11C8/12 ,  G06F12/00 ,  G06F13/1668

Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

Abstract translation: 一种存储器模块，包括：第一引脚，布置成接收第一信号; 布置成接收第二信号的第二引脚; 第一导电路径，其具有耦合到第一引脚的第一端; 至少一个存储器芯片，耦合到所述第一导电路径，用于接收所述第一信号; 预定的电阻器，具有耦合到第一导电路径的第二端的第一端子; 以及第二导电路径，其具有耦合到第二引脚的第一端，用于将第二端子传导到预定电阻器的第二端子; 其中所述第一信号和所述第二信号是同步的并且被配置为差分信号，用于使来自所述至少一个存储器芯片的所选择的存储器芯片被访问。

公开(公告)号：US11776613B2

公开(公告)日：2023-10-03

申请号：US17238000

申请日：2021-04-22

Applicant: MediaTek Inc.

Inventor： Bo-Wei Hsieh ,  Ching-Yeh Hsuan ,  Shang-Pin Chen

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/408 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G11C7/109 ,  G11C7/1093 ,  G11C11/408 ,  G11C11/4093 ,  G11C2207/2254

Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.

公开(公告)号：US11017839B2

公开(公告)日：2021-05-25

申请号：US15862884

申请日：2018-01-05

Applicant: MEDIATEK INC.

Inventor： Bo-Wei Hsieh ,  Ching-Yeh Hsuan ,  Shang-Pin Chen

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/408 ,  G11C7/10

Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.