公开(公告)号：US12189949B2

公开(公告)日：2025-01-07

申请号：US18049121

申请日：2022-10-24

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Tommaso Vali ,  Walter Di Francesco ,  Luigi Pilolli ,  Angelo Covello ,  Andrea D'Alessandro ,  Agostino Macerola ,  Cristina Lattaro ,  Claudia Ciaschi

IPC: G06F3/06

Abstract: In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.

公开(公告)号：US20240134571A1

公开(公告)日：2024-04-25

申请号：US18401251

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sivagnanam Parthasarathy ,  Patrick R. Khayat ,  Sundararajan Sankaranarayanan ,  Jeremy Binfet ,  Akira Goda

IPC: G06F3/06 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G11C16/26 ,  G11C16/0483

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.

公开(公告)号：US20240062828A1

公开(公告)日：2024-02-22

申请号：US18386919

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Robert W. Strong ,  William Akin ,  Jeremy Binfet

IPC: G11C16/16 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/16 ,  G11C16/30 ,  G11C16/26 ,  G11C16/102

Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

公开(公告)号：US20240055058A1

公开(公告)日：2024-02-15

申请号：US18229249

申请日：2023-08-02

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Liang Yu ,  Jonathan S. Parry

IPC: G11C16/30 ,  G11C5/06

CPC classification number: G11C16/30 ,  G11C5/06

Abstract: A memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a peak power management (PPM) token during a current PPM cycle, in response to receiving the PPM token, determining, based on a set of communication frequencies, whether to communicate auxiliary data to at least one other memory die during the current PPM cycle, wherein each communication frequency of the set of communication frequencies indicates when a respective type of auxiliary data is eligible for communication during a PPM cycle, and in response to determining to communicate auxiliary data to the at least one other memory die, causing a selected type of auxiliary data to be communicated to the at least one other memory die, wherein the selected type of auxiliary data is determined from the set of communication frequencies in view of the current PPM cycle.

公开(公告)号：US20230350587A1

公开(公告)日：2023-11-02

申请号：US18137002

申请日：2023-04-20

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Liang Yu ,  Jonathan S. Parry ,  Chulbum Kim ,  Daniel J. Hubbard ,  Suresh Rajgopal

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0658 ,  G06F3/0679

Abstract: A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include receiving a request to perform an operation, determining whether to initiate a PPM priority override procedure, and in response to determining to initiate the PPM priority override procedure, performing the PPM priority override procedure to execute the operation. Performing the PPM priority override procedure includes reconfiguring each high current breakpoints as a respective low current breakpoint to execute the operation.

公开(公告)号：US20230326527A1

公开(公告)日：2023-10-12

申请号：US17704154

申请日：2022-03-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Binfet ,  Kishore Kumar Muchherla

IPC: G11C16/04 ,  G11C16/32 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32

Abstract: Memories might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the memory to initiate an array operation on the array of memory cells, indicate an unavailability to initiate a next array operation, append a delay interval to an array access time of the array operation, and indicate an availability to initiate a next array operation in response to a completion of the delay interval. The delay interval might have a duration determined in response to an indication of temperature.

公开(公告)号：US11776629B2

公开(公告)日：2023-10-03

申请号：US16995517

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Niccolo' Righetti ,  Kishore K. Muchherla ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C16/10 ,  G11C16/14

CPC classification number: G11C16/10 ,  G11C16/14

Abstract: A method includes during a first portion of a service life of a memory device, programming at least one memory cell of the memory device to a first threshold voltage corresponding to a desired data state. The method can include during a second portion of the service life of the memory device subsequent to the first portion of the service life of the memory device, programming at least one memory cell of the memory device to a second threshold voltage corresponding to the desired data state. The second threshold voltage can be different than the first threshold voltage.

公开(公告)号：US11710525B2

公开(公告)日：2023-07-25

申请号：US17149048

申请日：2021-01-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C11/34 ,  G11C16/26 ,  G11C7/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/20 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B69/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/20 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B69/00

Abstract: Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.

公开(公告)号：US10916313B2

公开(公告)日：2021-02-09

申请号：US16574585

申请日：2019-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C7/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/20 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  H01L27/115

Abstract: Apparatus configured to establish a negative potential in a body of a memory cell during an access operation of another memory cell, and methods of operating such an apparatus, as well as apparatus configured to establish a negative potential in a body of a memory cell in response to a timer, or before a sensing operation of the memory cell.

公开(公告)号：US20180322930A1

公开(公告)日：2018-11-08

申请号：US16035933

申请日：2018-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/20 ,  G11C16/34 ,  H01L27/115 ,  G11C16/08 ,  G11C7/04 ,  G11C16/32 ,  G11C16/14 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/20 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.