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    FRACTIONAL BITS IN MEMORY CELLS
    12.
    发明申请
    FRACTIONAL BITS IN MEMORY CELLS 有权

    公开(公告)号：US20150206579A1

    公开(公告)日：2015-07-23

    申请号：US14599786

    申请日：2015-01-19

    Applicant: Micron Technology, Inc.

    Inventor： William H. Radke

    IPC: G11C11/56 ,  G06F11/10

    CPC classification number: G11C11/5628 ,  G06F11/1008 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C2211/5641

    Abstract: The present disclosure includes methods, devices, modules, and systems for programming memory cells. One method embodiment includes storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. The method also includes storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.

    POWER CONSUMPTION CONTROL
    13.
    发明申请
    POWER CONSUMPTION CONTROL 有权
    功耗控制

    公开(公告)号：US20150098291A1

    公开(公告)日：2015-04-09

    申请号：US14482408

    申请日：2014-09-10

    Applicant: Micron Technology, Inc.

    Inventor： Krishnam R. Datla ,  William H. Radke ,  Robin Sarno ,  Laszlo Borbely-Bartis ,  Ken Kannampuzha

    IPC: G11C5/14

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G11C5/14 ,  G11C16/30

    Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.

    Abstract translation: 本公开包括用于功耗控制的装置和方法。 多个实施例包括在命令的相位组合中确定每个阶段的功率消耗信息，并且至少部分地基于至少为至少确定的功耗信息授权执行组合中的至少一个相位的功率消耗信息 其中一个阶段。

    METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES
    14.
    发明申请
    METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES 有权
    用于调节设备中感应电压的方法，设备和系统

    公开(公告)号：US20140355355A1

    公开(公告)日：2014-12-04

    申请号：US14327913

    申请日：2014-07-10

    Applicant: Micron Technology, Inc.

    Inventor： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

    IPC: G11C16/28

    CPC classification number: G11C16/28 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26

    Abstract: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.

    Abstract translation: 本公开包括用于调整设备中的感测电压的方法，设备和系统。 一个或多个实施例包括存储器单元和被配置为使用感测电压对存储器单元执行感测操作的控制器，以确定具有大于感测电压的阈值电压（Vt）的存储器单元的数量并且调整感测电压 用于至少部分地基于所确定的存储器单元的数量来确定存储器单元的状态。

    MEMORY CELL COUPLING COMPENSATION
    15.
    发明申请
    MEMORY CELL COUPLING COMPENSATION 有权
    记忆体耦合补偿

    公开(公告)号：US20140233314A1

    公开(公告)日：2014-08-21

    申请号：US14182032

    申请日：2014-02-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhenlei Shen ,  William H. Radke ,  Peter Feeley

    IPC: G11C29/04 ,  G11C16/06

    CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F11/1048 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/04 ,  G11C29/52

    Abstract: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.

    Abstract translation: 描述了用于存储器单元耦合补偿的方法和被配置为执行其的装置。 用于存储单元耦合补偿的一种或多种方法包括使用根据第一存储单元耦合补偿电压而改变的电压来确定存储单元的状态，对存储单元的状态执行错误检查，以及确定状态 使用响应于错误检查失败的根据第二存储器单元耦合补偿电压而改变的电压的存储器单元。

    CORRECTING DATA IN A MEMORY
    16.
    发明申请
    CORRECTING DATA IN A MEMORY 有权
    校正记忆中的数据

    公开(公告)号：US20130332798A1

    公开(公告)日：2013-12-12

    申请号：US13964682

    申请日：2013-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Brady L. Keays ,  Shuba Swaminathan ,  William H. Radke

    IPC: G06F11/10

    CPC classification number: G06F11/10 ,  G06F11/1048 ,  H03M13/132 ,  H03M13/1515

    Abstract: Methods of correcting data in a memory, and memories adapted to correct data, include prioritizing error correction of the read data in response to locations and likely states of known bad or questionable data positions of a segment of a memory array selected for reading.

    Abstract translation: 校正存储器中的数据以及适于校正数据的存储器的方法包括响应于选择用于读取的存储器阵列的段的已知不良或可疑数据位置的位置和可能状态来优先考虑读取数据的错误校正。

    Memory devices having differently configured blocks of memory cells
    17.
    发明授权
    Memory devices having differently configured blocks of memory cells 有权

    公开(公告)号：US10891188B2

    公开(公告)日：2021-01-12

    申请号：US16516611

    申请日：2019-07-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

    IPC: G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C29/52

    Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of memory cells of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of memory cells of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of memory cells.

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