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    Method for forming an extended metal gate using a damascene process
    11.
    发明授权
    Method for forming an extended metal gate using a damascene process 有权
    使用镶嵌工艺形成延伸金属浇口的方法

    公开(公告)号：US06303447B1

    公开(公告)日：2001-10-16

    申请号：US09502036

    申请日：2000-02-11

    申请人： Vijai Komar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

    发明人： Vijai Komar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

    IPC分类号： H01L21336

    CPC分类号： H01L29/66545 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/41 ,  H01L29/42376 ,  H01L29/4941

    摘要： A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; wherein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

    摘要翻译： 一种用于形成不具有聚环绕效应的延伸金属栅极的方法。 提供其上具有栅极结构的半导体结构。 栅极结构包括依次堆叠的栅极介电层，栅极硅层，掺杂氧化硅层和一次性栅极层。 隔板形成在栅极结构的侧壁上。 在半导体结构和栅极结构之上形成电介质间隙填充层，并在一次性栅极层上停止平坦化。 在一次性栅极层上形成第一氮化硅层，并且在第一氮化硅层上形成电介质层。 图案化电介质层以在栅极结构上形成沟槽; 其中所述沟槽的宽度大于所述栅极结构的宽度。 使用一个或多个选择性蚀刻工艺去除沟槽底部中的第一氮化硅层和一次性栅极层。 使用掺杂的氧化硅对未掺杂的氧化硅具有高选择性的蚀刻来去除掺杂的氧化硅层。 在栅极硅层上形成阻挡层，在阻挡层上形成金属栅极层; 由此金属栅极层具有比栅极结构更大的宽度。

    Method to deposit a copper layer
    12.
    发明授权
    Method to deposit a copper layer 失效
    沉积铜层的方法

    公开(公告)号：US06261954B1

    公开(公告)日：2001-07-17

    申请号：US09501968

    申请日：2000-02-10

    申请人： Paul Kwok Keung Ho ,  Subhash Gupta ,  Mei Sheng Zhou ,  Simon Chooi

    发明人： Paul Kwok Keung Ho ,  Subhash Gupta ,  Mei Sheng Zhou ,  Simon Chooi

    IPC分类号： H01L2144

    CPC分类号： H01L21/76843 ,  C23C18/1608 ,  C25D7/123 ,  H01L21/288 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877

    摘要： A new method of depositing a copper layer, using disproportionation of Cu(I) ions from a solution stabilized by a polar organic solvent, for single and dual damascene interconnects in the manufacture of an integrated circuit device has been achieved. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer is patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer is deposited overlying the dielectric layer to line the vias and trenches. A simple Cu(I) ion solution, stabilized by a polar organic solvent, is coated overlying said barrier layer. Water is added to the stabilized simple Cu(I) ion solution to cause disproportionation of the simple Cu(I) ion from the Cu(I) ion solution. A copper layer is deposited overlying the barrier layer. The copper layer may comprise a thin seed layer for use in subsequent electroplating or electroless plating of copper or may comprise a thick copper layer to fill the vias and trenches. The integrated circuit is completed.

    摘要翻译： 已经实现了在制造集成电路器件中使用Cu（I）离子从由极性有机溶剂稳定的溶液中进行歧化的单层和双镶嵌互连的沉积铜层的新方法。 提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。 图案化电介质层以形成用于计划的双镶嵌互连的通孔和沟槽。 沉积覆盖在介电层上的阻挡层以对通孔和沟槽进行排列。 将由极性有机溶剂稳定的简单的Cu（I）离子溶液涂覆在所述阻挡层上。 向稳定化的简单的Cu（I）离子溶液中加入水以引起Cu（I）离子溶液中简单的Cu（I）离子的歧化。 沉积在屏障层上的铜层。 铜层可以包括用于铜的后续电镀或无电镀的薄种子层，或者可以包括用于填充通孔和沟槽的厚铜层。 集成电路完成。

    Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
    13.
    发明授权
    Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer 有权
    使用碳氮化物，氮化硼或氮化硼钝化层，蚀刻停止层和/或覆盖层的具有降低的电容的镶嵌结构

    公开(公告)号：US06165891A

    公开(公告)日：2000-12-26

    申请号：US435434

    申请日：1999-11-22

    申请人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

    发明人： Simon Chooi ,  Yi Xu ,  Mei Sheng Zhou

    IPC分类号： H01L21/311 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  G03C5/00 ,  H01L21/302 ,  H01L23/48

    CPC分类号： H01L21/76835 ,  H01L21/31122 ,  H01L21/318 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by providing a semiconductor structure having a first conductive layer thereover. A passivation layer is formed on the first conductive layer. A first dielectric layer is formed over the passivation layer, and an etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer, and an optional cap layer can be formed over the second dielectric layer. The cap layer, the second dielectric layer, the etch stop layer, and the first dielectric layer are patterned to form a via opening stopping on said passivation layer and a trench opening stopping on the first conductive layer. A carbon nitride passivation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen atmosphere. A boron nitride passivation layer, etch stop layer, or cap layer can be formed by PECVD using B.sub.2 H.sub.6, ammonia, and nitrogen. A boron carbon nitride passivatation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen and B.sub.2 H.sub.6 atmosphere.

    摘要翻译： 通过使用包含碳氮化物，氮化硼或碳氮化硼的低介电常数材料通过形成钝化层，蚀刻停止层和盖层中的一个或多个来形成具有降低的电容的镶嵌结构的方法和结构。 该方法开始于提供其上具有第一导电层的半导体结构。 在第一导电层上形成钝化层。 第一电介质层形成在钝化层之上，并且在第一介电层上形成蚀刻停止层。 第二介电层形成在蚀刻停止层上方，并且可以在第二介电层上形成任选的盖层。 图案化盖层，第二电介质层，蚀刻停止层和第一介电层，以形成在所述钝化层上停止的通孔开口和在第一导电层上停止的沟槽开口。 碳氮化物钝化层，蚀刻停止层或盖层可以通过在氮气气氛中的石墨靶磁控溅射来形成。 可以通过使用B2H6，氨和氮的PECVD形成氮化硼钝化层，蚀刻停止层或盖层。 硼氮化物钝化层，蚀刻停止层或盖层可以通过在氮气和B2H6气氛中的石墨靶的磁控溅射形成。

    Dual metal gate process: metals and their silicides
    15.
    发明授权
    Dual metal gate process: metals and their silicides 有权

    公开(公告)号：US07005716B2

    公开(公告)日：2006-02-28

    申请号：US10853454

    申请日：2004-05-25

    申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

    发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/66545 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/517

    摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

    Dual metal gate process: metals and their silicides
    17.
    发明授权
    Dual metal gate process: metals and their silicides 有权
    双金属栅极工艺：金属及其硅化物

    公开(公告)号：US06750519B2

    公开(公告)日：2004-06-15

    申请号：US10266714

    申请日：2002-10-08

    申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

    发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

    IPC分类号： H01L2976

    CPC分类号： H01L29/66545 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/517

    摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

    摘要翻译： 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将硅离子注入到一个有源区域中的金属层中以形成硅化物以形成金属硅化物层的注入金属层。 此后，金属层和金属硅化物层被图案化以在一个有源区域中形成金属栅极，在另一个有源区域中形成金属硅化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属硅化物栅极，其中两个栅极的硅浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是硅植入和硅化的。 PMOS栅极具有较高的功函数。

    Method of using silicon rich carbide as a barrier material for fluorinated materials
    18.
    发明授权
    Method of using silicon rich carbide as a barrier material for fluorinated materials 失效
    使用富碳化碳作为氟化材料的阻挡材料的方法

    公开(公告)号：US06730591B2

    公开(公告)日：2004-05-04

    申请号：US10186532

    申请日：2002-07-01

    申请人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

    发明人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

    IPC分类号： H01L214763

    CPC分类号： H01L21/76834 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3127 ,  H01L21/314 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

    摘要： A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

    摘要翻译： 一种在半导体器件中形成互连结构的方法，包括以下步骤。 提供半导体结构。 在第一实施例中，在半导体结构上形成至少一条金属线。 在金属线和半导体结构之上形成富含碳的碳化物阻挡层。 最后，在富含硅的碳化物层上形成可被氟化的介电层。 在第二实施例中，在半导体结构上形成至少一个可被氟化的氟化介电层。 图案化电介质层以在其中形成开口。 在开口内形成富含碳的碳化物阻挡层。 在结构上沉积金属化层，填充富含硅的碳化物阻挡层衬里的开口。 最后，金属化层可以被平坦化以在富含硅的碳化物阻挡层衬里的开口内形成平坦化的金属结构。

    Method to improve etching of organic-based, low dielectric constant materials
    20.
    发明授权
    Method to improve etching of organic-based, low dielectric constant materials 失效
    改善有机系低介电常数材料蚀刻的方法

    公开(公告)号：US06524963B1

    公开(公告)日：2003-02-25

    申请号：US09421510

    申请日：1999-10-20

    申请人： Mei Sheng Zhou ,  Simon Chooi ,  Jian Xun Li

    发明人： Mei Sheng Zhou ,  Simon Chooi ,  Jian Xun Li

    IPC分类号： H01L21302

    CPC分类号： H01L21/31116 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/76802

    摘要： A method etching an organic-based, low dielectric constant material in the manufacture of an integrated circuit device has been achieved. Organic materials without silicon and organic materials without fluorine can be etched by using, for example, hydrazine or ammonia gas. Organic materials with silicon can also be etched with the addition of a fluorine-containing or chlorine-containing gas. A semiconductor substrate is provided. A low dielectric constant organic-based material is deposited overlying the semiconductor substrate. The low dielectric constant organic-based material is etched to form desirable features using a plasma containing a gas comprising a nitrogen and hydrogen containing molecule, and the integrated circuit device is completed.

    摘要翻译： 已经实现了在制造集成电路器件中蚀刻有机基低介电常数材料的方法。 不含硅的有机材料和无氟的有机材料可以通过使用例如肼或氨气进行蚀刻。 也可以通过添加含氟或含氯气体来蚀刻具有硅的有机材料。 提供半导体衬底。 沉积在半导体衬底上的低介电常数有机基材料。 使用包含含有氮和氢的分子的气体的等离子体来蚀刻低介电常数有机基材料以形成期望的特征，并且完成集成电路器件。