公开(公告)号：US20070259481A1

公开(公告)日：2007-11-08

申请号：US11778659

申请日：2007-07-17

申请人： Chih-Ming Chung

发明人： Chih-Ming Chung

IPC分类号： H01L21/58

CPC分类号： H01L21/563 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/11822 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/1357 ,  H01L2224/1369 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81355 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2224/83191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K3/3436 ,  H05K3/3489 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/05099

摘要： A process for fabricating a chip package structure with the following steps is provided. First, a chip having an active surface is provided. A plurality of solder bumps is disposed on the active surface. Then, a polymer material including flux is placed on the surface of the solder bumps by a dipping process. The chip is disposed on a carrier such that the carrier is in contact with the solder bumps. A reflow process is carried out so that the chip and the carrier are electrically connected through the solder bumps and a plurality of supporting structures made from the polymer material are formed around the junctions between the solder bumps and the carrier. The supporting structures enhance the endurance of the solder bumps to thermal stress and reduce damage due to fatigue.

摘要翻译： 提供了以下步骤制造芯片封装结构的工艺。 首先，提供具有活性表面的芯片。 多个焊料凸块设置在有源表面上。 然后，通过浸渍处理将包含焊剂的聚合物材料放置在焊料凸块的表面上。 芯片设置在载体上，使得载体与焊料凸块接触。 进行回流处理，使得芯片和载体通过焊料凸块电连接，并且由聚合物材料制成的多个支撑结构形成在焊料凸块和载体之间的接合部周围。 支撑结构增强了焊料凸块对热应力的耐久性，并减少了由于疲劳造成的损坏。

公开(公告)号：US07125745B2

公开(公告)日：2006-10-24

申请号：US10833087

申请日：2004-04-28

申请人： Kun-Ching Chen ,  Yi-Chuan Ding ,  Po-Jen Cheng ,  Chih-Ming Chung ,  Yun-Hsiang Tien

发明人： Kun-Ching Chen ,  Yi-Chuan Ding ,  Po-Jen Cheng ,  Chih-Ming Chung ,  Yun-Hsiang Tien

IPC分类号： H01L21/44

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/11 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

摘要： A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

摘要翻译： 用于倒装芯片凸块和引线接合应用的多芯片封装衬底包括具有顶表面和底表面的衬底本体。 多个凸台和多个引线接合垫形成在顶表面上。 凸起垫设置在基板主体的顶表面上，并且在凸起的焊盘上形成预焊材料。 引线接合焊盘设置在基板主体的顶表面上，并且在引线接合焊盘上形成Ni / Au层。 为了避免在包装过程中碰撞垫和引线接合垫发生氧化。 预焊材料完全覆盖凸块，以避免在包装过程中在凸起芯片上的多个凸块中产生的Au金属间化合物。 用于倒装芯片凸块和引线接合应用的多芯片堆叠封装的可靠性将大大提高。

公开(公告)号：US08546950B2

公开(公告)日：2013-10-01

申请号：US12947390

申请日：2010-11-16

申请人： Shin-Hua Chao ,  Chao-Yuan Liu ,  Hui-Ying Hsieh ,  Chih-Ming Chung

发明人： Shin-Hua Chao ,  Chao-Yuan Liu ,  Hui-Ying Hsieh ,  Chih-Ming Chung

IPC分类号： H01L23/48

CPC分类号： H01L24/96 ,  H01L21/56 ,  H01L23/145 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.

摘要翻译： 提供半导体封装及其制造方法。 半导体封装包括衬底，半导体元件，封装体和导电部件。 基板具有电接触。 半导体元件设置在基板上。 封装体覆盖半导体元件并且限定了电触头暴露的通孔。 其中，包装体包括树脂体和多个纤维层。 纤维层设置在树脂体中并限定多个布置成阵列的纤维孔。 导电部件通过通孔与基板电连接。

公开(公告)号：US08546932B1

公开(公告)日：2013-10-01

申请号：US13586375

申请日：2012-08-15

申请人： Chih-Ming Chung

发明人： Chih-Ming Chung

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/315 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00

摘要： A PoP (package-on-package) package includes a bottom package with a substrate encapsulated in an encapsulant with a die coupled to the top of the substrate. At least a portion of the die is exposed above the encapsulant on the bottom package substrate. A top package includes a substrate with encapsulant on both the frontside and the backside of the substrate. The backside of the top package substrate is coupled to the topside of the bottom package substrate with at least part of the die being located in a recess in the encapsulant on the backside of the top package substrate.

摘要翻译： PoP（封装封装）封装包括底部封装，其具有封装在具有与基板顶部耦合的管芯的密封剂中的基板。 裸片的至少一部分暴露在底部封装衬底上的密封剂上方。 顶部封装包括在衬底的前侧和后侧上具有密封剂的衬底。 顶部封装衬底的背面耦合到底部封装衬底的顶部，其中模具的至少一部分位于封装材料的位于顶部封装衬底的背面上的凹部中。

公开(公告)号：US07834469B2

公开(公告)日：2010-11-16

申请号：US12428277

申请日：2009-04-22

申请人： Yao-Kai Chuang ,  Chien Liu ,  Chih-Ming Chung ,  Chao-Cheng Liu

发明人： Yao-Kai Chuang ,  Chien Liu ,  Chih-Ming Chung ,  Chao-Cheng Liu

IPC分类号： H01L23/29

CPC分类号： H01L23/49548 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/03 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second leads have a second upper surface which is not co-planar with the first upper surface. The chip package is disposed on the first leads and includes a substrate, a first chip, and a first molding compound. The second chip is stacked on the chip package and electrically connected to the second leads. The second molding compound is disposed on the lead frame and filled among the first leads and the second leads for encapsulating the chip package and the second chip.

摘要翻译： 提供了包括引线框架，芯片封装，第二芯片和第二模塑料的堆叠式芯片封装结构。 引线框架包括彼此绝缘的多个第一引线和第二引线。 第一引线具有第一上表面，并且第二引线具有与第一上表面不共面的第二上表面。 芯片封装设置在第一引线上并且包括基板，第一芯片和第一模塑料。 第二芯片堆叠在芯片封装上并电连接到第二引线。 第二模塑料设置在引线框架上，并且填充在第一引线和用于封装芯片封装和第二芯片的第二引线之间。

公开(公告)号：US20100213598A1

公开(公告)日：2010-08-26

申请号：US12683613

申请日：2010-01-07

申请人： Chien Liu ,  Chih-Ming Chung

发明人： Chien Liu ,  Chih-Ming Chung

IPC分类号： H01L23/482 ,  H05K1/09

CPC分类号： H05K3/3452 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/498 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/0315 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A circuit carrier suitable for being connected with a bump is provided. The circuit carrier includes a substrate and at least one bonding pad. The substrate has a bonding pad disposed on a surface thereof for being connected with the bump. A brown-oxide layer is disposed on a surface of the bonding pad.

摘要翻译： 提供适于与凸块连接的电路载体。 电路载体包括衬底和至少一个接合焊盘。 衬底具有设置在其表面上用于与凸块连接的接合焊盘。 在接合焊盘的表面上设置有棕色氧化物层。

公开(公告)号：US20090278243A1

公开(公告)日：2009-11-12

申请号：US12429476

申请日：2009-04-24

申请人： Yao-Kai Chuang ,  Chih-Ming Chung ,  Chien Liu ,  Chao-Cheng Liu

发明人： Yao-Kai Chuang ,  Chih-Ming Chung ,  Chien Liu ,  Chao-Cheng Liu

IPC分类号： H01L23/52 ,  H01L21/98

CPC分类号： H01L21/4832 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked type chip package structure including a chip carrier, a first chip, a second chip, a third chip, and an insulating material is provided. The chip carrier includes two die pads and a plurality of leads surrounding the die pads. The first chip and the second chip are disposed on the die pads respectively, and are electrically connected to the leads by wire bonding. The third chip traverses the first chip and the second chip, and is electrically connected to the first chip and the second chip respectively. The insulating material is disposed on the chip carrier for encapsulating the first chip, the second chip and the third chip, and fills among the die pads and the leads.

摘要翻译： 提供了包括芯片载体，第一芯片，第二芯片，第三芯片和绝缘材料的堆叠型芯片封装结构。 芯片载体包括两个管芯焊盘和围绕焊盘的多个引线。 第一芯片和第二芯片分别设置在芯片焊盘上，并且通过引线接合电连接到引线。 第三芯片穿过第一芯片和第二芯片，分别电连接到第一芯片和第二芯片。 绝缘材料设置在芯片载体上，用于封装第一芯片，第二芯片和第三芯片，并且填充在芯片焊盘和引线之间。

公开(公告)号：US20070085218A1

公开(公告)日：2007-04-19

申请号：US11563029

申请日：2006-11-24

申请人： Yu-Wen Chen ,  Chih-Ming Chung ,  Chi-Hao Chiu

发明人： Yu-Wen Chen ,  Chih-Ming Chung ,  Chi-Hao Chiu

IPC分类号： H01L23/48

CPC分类号： H01L24/28 ,  H01L21/563 ,  H01L23/36 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599

摘要： A flip chip package structure is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

摘要翻译： 提供了一种倒装芯片封装结构。 芯片电连接到基板。 散热片连接到芯片的背面。 散热器至少具有位于周边区域并且横向邻近芯片的通孔。 进行分配处理以通过通孔输送底部填充材料，使得填充芯片和基板之间的空间。 底部填充材料还延伸以覆盖散热器的一部分，使得散热器和基板连接在一起。 固化底部填充材料以将散热器，基板和芯片固定就位。

公开(公告)号：US07098071B2

公开(公告)日：2006-08-29

申请号：US11136181

申请日：2005-05-24

申请人： Ming-Lun Ho ,  Chih-Ming Chung

发明人： Ming-Lun Ho ,  Chih-Ming Chung

IPC分类号： H01L21/44

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2224/0401

摘要： The present invention relates to a method for flip chip bonding by utilizing an interposer with embedded bumps. The method comprises (a) providing a first element having a first surface; (b) forming an interposer onto the first surface; (c) forming a plurality of openings on the interposer; (d) forming a plurality of bumps in the openings, wherein the height of the bumps is smaller than the depth of the openings; (e) providing a second element having a plurality of pre-solders; and (f) bonding the first surface onto the second element, so that the pre-solders are disposed in the openings and in contact with the bumps. As a result, the self-alignment between the pre-solders and the bumps can avoid the shift between the first element and the second element.

公开(公告)号：US20050275080A1

公开(公告)日：2005-12-15

申请号：US10854131

申请日：2004-05-26

申请人： Chih-Ming Chung

发明人： Chih-Ming Chung

IPC分类号： H01L23/02 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2224/05599

摘要： The present invention relates to a multi-chip module package structure including a substrate with at least a slot, at least a first and a second chips and a molding compound. The first chip is larger than the second chip. The two chips are respectively disposed on two opposite surfaces of the substrate, while the slot exposes the bonding pads of the first chip. The bonding pads of the first chip are electrically connected to the top surface of the substrate by wire bonding. The second chip is electrically attached to the substrate by flip chip bonding or wire bonding. The molding compound at least covers the first and second chips and a portion of the substrate.

摘要翻译： 本发明涉及一种多芯片模块封装结构，其包括具有至少一个狭缝的基板，至少第一和第二芯片以及模塑料。 第一个芯片比第二个芯片大。 两个芯片分别设置在基板的两个相对表面上，而槽暴露第一芯片的焊盘。 第一芯片的焊盘通过引线接合电连接到衬底的顶表面。 第二芯片通过倒装芯片接合或引线接合电连接到基板。 成型化合物至少覆盖第一和第二芯片和基板的一部分。