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141 条记录 (耗时 0.037 秒)

    Sensing product and method of making
    13.
    发明授权
    Sensing product and method of making 有权
    感知产品和制作方法

    公开(公告)号：US09419155B2

    公开(公告)日：2016-08-16

    申请号：US13343922

    申请日：2012-01-05

    申请人： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

    发明人： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC分类号： H01L31/0232 ,  H01L31/101 ,  H01L31/18

    CPC分类号： H01L31/0232 ,  H01L31/02327 ,  H01L31/101 ,  H01L31/18

    摘要： This description relates to a sensing product formed using a substrate with a plurality of epi-layers. At least a first epi-layer has a different composition than the composition of a second epi-layer. The sensing product optionally includes at least one radiation sensing element in the second epi-layer and optionally an interconnect structure over the second epi-layer. The sensing product is formed by removing the substrate and all epi-layers other than the second epi-layer. A light incident surface of the second epi-layer has a total thickness variation of less than about 0.15 μm.

    摘要翻译： 该描述涉及使用具有多个外延层的基板形成的感测产品。 至少第一外延层具有与第二外延层的组成不同的组成。 感测产品可选地包括第二外延层中的至少一个辐射感测元件以及可选地在第二外延层上的互连结构。 通过去除衬底和除第二外延层之外的所有外延层形成传感产物。 第二外延层的光入射表面具有小于约0.15μm的总厚度变化。

    Method and Apparatus for Backside Illumination Sensor
    14.
    发明申请
    Method and Apparatus for Backside Illumination Sensor 有权
    背面照明传感器的方法和装置

    公开(公告)号：US20130228886A1

    公开(公告)日：2013-09-05

    申请号：US13409924

    申请日：2012-03-01

    申请人： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L31/0232 ,  H01L31/18

    CPC分类号： H01L27/1464 ,  H01L27/14687

    摘要： Methods and apparatus for a backside illuminated (BSI) image sensor device are disclosed. A BSI sensor device is formed on a substrate comprising a photosensitive diode. The substrate may be thinned at the backside, then a B doped Epi-Si(Ge) layer may be formed on the backside surface of the substrate. Additional layers may be formed on the B doped Epi-Si(Ge) layer, such as a metal shield layer, a dielectric layer, a micro-lens, and a color filter.

    摘要翻译： 公开了用于背面照明（BSI）图像传感器装置的方法和装置。 在包括感光二极管的基板上形成BSI传感器装置。 衬底可以在背面变薄，则可以在衬底的背面上形成B掺杂的Epi-Si（Ge）层。 另外的层可以形成在B掺杂的Epi-Si（Ge）层上，例如金属屏蔽层，电介质层，微透镜和滤色器。

    Via/contact and damascene structures and manufacturing methods thereof
    15.
    发明授权
    Via/contact and damascene structures and manufacturing methods thereof 有权
    通孔/接触和镶嵌结构及其制造方法

    公开(公告)号：US08247322B2

    公开(公告)日：2012-08-21

    申请号：US11680981

    申请日：2007-03-01

    申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76831 ,  H01L21/7684

    摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

    摘要翻译： 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。

    Apparatuses for electrochemical deposition, conductive layer, and fabrication methods thereof
    17.
    发明授权
    Apparatuses for electrochemical deposition, conductive layer, and fabrication methods thereof 有权
    电化学沉积装置，导电层及其制造方法

    公开(公告)号：US07837841B2

    公开(公告)日：2010-11-23

    申请号：US11686504

    申请日：2007-03-15

    申请人： Kei-Wei Chen ,  Mu-Han Cheng ,  Jian-Sin Tsai ,  Ying-Lang Wang

    发明人： Kei-Wei Chen ,  Mu-Han Cheng ,  Jian-Sin Tsai ,  Ying-Lang Wang

    IPC分类号： C25D5/00 ,  C25D5/18 ,  C25D17/00 ,  C25B15/00

    CPC分类号： C25D17/001 ,  C25D17/007 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  Y10T428/16

    摘要： Electrochemical plating (ECP) apparatuses with auxiliary cathodes to create uniform electric flux density. An ECP apparatus for electrochemical deposition includes an electrochemical cell with an electrolyte bath for electrochemically depositing a metal on a substrate. A main cathode and an anode are disposed in the electrolyte bath to provide a main electrical field. A substrate holder assembly holds a semiconductor wafer connecting the cathode. An auxiliary cathode is disposed outside the electrochemical cell to provide an auxiliary electrical field such that a flux line density at the center region of the substrate holder assembly substantially equals that at the circumference of the substrate holder assembly.

    摘要翻译： 具有辅助阴极的电化学电镀（ECP）装置，以产生均匀的电流密度。 用于电化学沉积的ECP设备包括具有用于在基底上电化学沉积金属的电解质浴的电化学电池。 主阴极和阳极设置在电解槽中以提供主电场。 衬底保持器组件保持连接阴极的半导体晶片。 辅助阴极设置在电化学电池外部以提供辅助电场，使得衬底保持器组件的中心区域处的磁通线密度基本上等于衬底保持器组件的圆周处的磁通密度。

    Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch
    19.
    发明申请
    Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch 审中-公开
    使用净沉积和净蚀刻在纳米沟槽结构中形成种子层

    公开(公告)号：US20090127097A1

    公开(公告)日：2009-05-21

    申请号：US11941435

    申请日：2007-11-16

    申请人： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Sheng Wang ,  Szu-An Wu ,  Ying-Lang Wang

    发明人： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Sheng Wang ,  Szu-An Wu ,  Ying-Lang Wang

    IPC分类号： C23C14/00

    CPC分类号： C23C14/345 ,  C23C14/046 ,  H01L21/76862 ,  H01L21/76873

    摘要： A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a net deposition step to form a seed layer having a portion in the opening, wherein the net deposition step comprises a first deposition and a first etching; performing a net etch step to the seed layer, wherein the net etch step comprises a first etching and a first deposition, wherein a portion of the seed layer remains after the net etch step; and growing a conductive material on the seed layer to fill a remaining portion of the opening.

    摘要翻译： 形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行净沉积步骤以形成具有在开口中的一部分的种子层，其中所述净沉积步骤包括第一沉积和第一蚀刻; 对所述种子层进行净蚀刻步骤，其中所述净蚀刻步骤包括第一蚀刻和第一沉积，其中所述种子层的一部分在所述净蚀刻步骤之后保留; 以及在种子层上生长导电材料以填充开口的剩余部分。

    Copper plating of semiconductor devices using single intermediate low power immersion step
    20.
    发明授权
    Copper plating of semiconductor devices using single intermediate low power immersion step 有权
    采用单中级低功耗浸入式半导体器件镀铜

    公开(公告)号：US07312149B2

    公开(公告)日：2007-12-25

    申请号：US10840095

    申请日：2004-05-06

    申请人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

    发明人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

    IPC分类号： H01L21/44

    CPC分类号： C25D7/123 ,  C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  H01L21/2885

    摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

    摘要翻译： 在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀 从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。 第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。 低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。