公开(公告)号：US20240379596A1

公开(公告)日：2024-11-14

申请号：US18660210

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Terrence B. McDaniel ,  Kunal R. Parekh ,  Bret K. Street ,  Akshay N. Singh

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A through via extends entirely through the substrate. The through via includes a protruding portion that extends beyond the back side of the substrate. A layer of silicon carbon nitride is disposed at the back side of the substrate and along sidewalls of the protruding portion of the through via. A layer of oxide is disposed at the back side of the substrate and at least partially surrounding the protruding portion of the through via. A conductive pad is disposed at a coupling surface of the through via and at least partially extending through the layer of oxide. As a result, a reliable and cost-efficient semiconductor device can be assembled.

公开(公告)号：US20220165701A1

公开(公告)日：2022-05-26

申请号：US17103834

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

公开(公告)号：US12278202B2

公开(公告)日：2025-04-15

申请号：US17830224

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Bret K. Street ,  Debjit Datta ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/00

Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

公开(公告)号：US20240339433A1

公开(公告)日：2024-10-10

申请号：US18610268

申请日：2024-03-20

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Nevil N. Gajera ,  Akshay N. Singh ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L23/31 ,  H01L23/481 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/19 ,  H01L2224/21 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06548

Abstract: A semiconductor device with a through dielectric via is disclosed. The semiconductor device assembly can include a semiconductor die and multiple stacks of semiconductor dies coupled with the semiconductor die at different lateral locations. Dielectric material can be disposed at the semiconductor die between the multiple stacks of semiconductor dies. The through dielectric via can extend entirely through the dielectric material to the semiconductor die such that the through dielectric via couples with circuitry at the semiconductor die. In this way, the through dielectric via can provide power to the semiconductor die (e.g., exclusive of the multiple stacks of semiconductor dies).

公开(公告)号：US20240297149A1

公开(公告)日：2024-09-05

申请号：US18426271

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a logic die, a top memory die, and a one or more intermediate memory dies between the top memory die and the logic die. Front sides of the one or more intermediate memory dies at which active circuitry is disposed face a front side of the top memory die. Back sides of the one or more intermediate memory dies opposite the front sides face a back side of the logic die. In doing so, a cost-efficient, low-complexity semiconductor device can be assembled.

公开(公告)号：US20240282731A1

公开(公告)日：2024-08-22

申请号：US18406068

申请日：2024-01-05

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Wei Zhou ,  Debjit Datta ,  Chaiyanan Kulchaisit ,  Kyle K. Kirby ,  Akshay N. Singh

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L24/08 ,  H01L21/56 ,  H01L23/295 ,  H01L24/05 ,  H01L24/13 ,  H01L24/80 ,  H01L2224/02379 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor device assembly, including a semiconductor die having a frontside surface, a first plurality of bond pads at the frontside surface and a first dielectric layer at the frontside surface; and an interface die having a frontside surface and a backside surface, the interface die including a second plurality of bond pads and a second dielectric layer disposed on the backside surface of the interface die, a third dielectric layer disposed on the frontside surface of the interface die, wherein the third dielectric layer includes a mechanically altered surface opposite the frontside surface of the interface die, and a redistribution layer disposed on the third dielectric layer and above the frontside surface of the interface die, wherein hybrid bonds are disposed between the frontside surface of the semiconductor die and the backside surface of the interface die.

公开(公告)号：US11678483B2

公开(公告)日：2023-06-13

申请号：US17160956

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  H10B41/27 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H10B41/35 ,  H10B41/41 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/27 ,  G06F3/0688 ,  G11C8/14 ,  G11C16/0466 ,  H10B41/35 ,  H10B41/41 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

公开(公告)号：US11672114B2

公开(公告)日：2023-06-06

申请号：US17396952

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  David Daycock ,  Subramanian Krishnan ,  Leroy Ekarista Wibowo

IPC: H10B41/27 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35 ,  H10B43/40 ,  H01L21/311 ,  H01L21/3213 ,  H10B41/40 ,  H10B43/10 ,  H10B41/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11519

CPC classification number: H01L27/11556 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material. The first and second insulator materials comprise different compositions relative one another. Conductive vias are formed in the second insulator material that are individually directly electrically coupled to the individual channel-material strings through the upwardly-projecting conducting material. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230048311A1

公开(公告)日：2023-02-16

申请号：US17666437

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Keizo Kawakita ,  Bret K. Street

IPC: H01L23/00 ,  H01L25/065

Abstract: Bond pads for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bond pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bond pad on a second side of the second semiconductor die. The first bond pad is aligned and bonded to the second bond pad at a bonding interface between the first and second bond pads, and at least one of the first and second bond pads include a first metal and a second metal different than the first metal. Further, the first metal is located at the bonding interface and the second metal has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.

公开(公告)号：US20230026960A1

公开(公告)日：2023-01-26

申请号：US17956797

申请日：2022-09-29

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.