中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

125 records (took 0.051 seconds)

    Integrated Structures and Methods of Forming Integrated Structures
    15.
    发明申请
    Integrated Structures and Methods of Forming Integrated Structures 有权

    公开(公告)号：US20170141119A1

    公开(公告)日：2017-05-18

    申请号：US14942823

    申请日：2015-11-16

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu ,  Allen McTeer

    IPC: H01L27/115 ,  H01L21/322 ,  H01L21/02

    CPC classification number: H01L27/11524 ,  H01L21/02672 ,  H01L21/3221 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.

    Methods Of Forming Transistor Gates
    16.
    发明申请
    Methods Of Forming Transistor Gates 有权
    形成晶体管门的方法

    公开(公告)号：US20160322478A1

    公开(公告)日：2016-11-03

    申请号：US15207275

    申请日：2016-07-11

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu

    IPC: H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  H01L21/28 ,  H01L27/115

    CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/792

    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in Which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

    Abstract translation: 一些实施例包括形成电荷存储晶体管栅极和标准FET栅极的方法，其中共同处理用于制造不同类型栅极的至少一些部分。 可以形成FET和电荷存储晶体管栅极堆叠。 栅极堆叠可以各自包括栅极材料，绝缘材料和牺牲材料。 牺牲材料从FET中去除并对存储晶体管栅极堆叠进行充电。 FET栅极堆叠的绝缘材料被蚀刻通过。 导电材料形成在FET栅叠层上方和电荷存储晶体管栅堆上。 导电材料物理地接触FET栅极堆叠的栅极材料，并且通过残留在电荷存储晶体管栅极堆叠中的绝缘材料与电荷存储晶体管栅极堆叠的栅极材料分离。 一些实施例包括门结构。

    Semiconductor Devices, and Methods of Forming Semiconductor Devices
    17.
    发明申请
    Semiconductor Devices, and Methods of Forming Semiconductor Devices 有权
    半导体器件和半导体器件的形成方法

    公开(公告)号：US20160211324A1

    公开(公告)日：2016-07-21

    申请号：US14597766

    申请日：2015-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Shu Qin ,  Yongjun Jeff Hu ,  Allen McTeer

    IPC: H01L29/08 ,  H01L21/223 ,  H01L27/092 ,  H01L29/45

    CPC classification number: H01L29/0847 ,  H01L21/2236 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/823418 ,  H01L27/092 ,  H01L29/456 ,  H01L29/665

    Abstract: Some embodiments include a device having an n-type diffusion region, and having a boron-doped region within the n-type diffusion region. The boron-doped region extends no deeper than about 10 nanometers from an upper surface of the n-type diffusion region. Some embodiments include a method in which first boron-enhanced regions are formed within upper portions of n-type source/drain regions of an NMOS (n-type metal-oxide-semiconductor) device and second boron-enhanced regions are simultaneously formed within upper portions of p-type source/drain regions of a PMOS (p-type metal-oxide-semiconductor) device. The first and second boron-enhanced regions extend to depths of less than or equal to about 10 nanometers.

    Abstract translation: 一些实施例包括具有n型扩散区的器件，并且在n型扩散区内具有硼掺杂区。 硼掺杂区从n型扩散区的上表面延伸不超过约10纳米。 一些实施例包括其中在NMOS（n型金属氧化物 - 半导体）器件的n型源极/漏极区的上部形成第一硼增强区的方法，并且第二硼增强区同时形成在上部 PMOS（p型金属氧化物半导体）器件的p型源/漏区的部分。 第一和第二硼增强区域延伸到小于或等于约10纳米的深度。

    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS
    20.
    发明申请
    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS 有权
    相位变化的存储堆栈与处理的SIDEWALLS

    公开(公告)号：US20150318468A1

    公开(公告)日：2015-11-05

    申请号：US14266415

    申请日：2014-04-30

    Applicant: Micron Technology, Inc.

    Inventor： Tsz W. Chan ,  Yongjun Jeff Hu ,  Swapnil Lengade ,  Shu Qin ,  Everett Allen McTeer

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1675

    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

    Abstract translation: 已经公开了用于制造存储器件的存储器件和方法。 一种这样的方法包括从多个元件形成存储器堆叠。 在存储器堆叠的至少一个侧壁上形成粘附物质，其中粘附物质具有梯度结构，其导致粘附物质与存储器堆叠的元件混合以终止元件的不满足的原子键。 梯度结构还包括在至少一个侧壁的外表面上的粘附物质的膜。 将电介质材料注入到粘附物质的膜中以形成侧壁衬里。

Patent Agency Ranking