公开(公告)号：US11705385B2

公开(公告)日：2023-07-18

申请号：US17367990

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Chet E. Carter ,  Anilkumar Chandolu ,  Justin B. Dorhout ,  Jun Fang ,  Matthew J. King ,  Brett D. Lowe ,  Matthew Park ,  Justin D. Shepherdson

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/28 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27

CPC classification number: H01L23/481 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

公开(公告)号：US11605642B2

公开(公告)日：2023-03-14

申请号：US17124313

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Brett D. Lowe

IPC: H01L27/11556 ,  H01L23/528 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11177279B2

公开(公告)日：2021-11-16

申请号：US16876896

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11573

Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

公开(公告)号：US11069598B2

公开(公告)日：2021-07-20

申请号：US16444634

申请日：2019-06-18

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Chet E. Carter ,  Anilkumar Chandolu ,  Justin B. Dorhout ,  Jun Fang ,  Matthew J. King ,  Brett D. Lowe ,  Matthew Park ,  Justin D. Shepherdson

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

公开(公告)号：US10985179B2

公开(公告)日：2021-04-20

申请号：US16532019

申请日：2019-08-05

Applicant: Micron Technology, inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L27/115 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20200279867A1

公开(公告)日：2020-09-03

申请号：US16876896

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11573

Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

公开(公告)号：US10269819B2

公开(公告)日：2019-04-23

申请号：US15497009

申请日：2017-04-25

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gordon A. Haller ,  Charles H. Dennison ,  Anish A. Khandekar ,  Brett D. Lowe ,  Lining He ,  Brian Cleereman

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.

公开(公告)号：US10141330B1

公开(公告)日：2018-11-27

申请号：US15606415

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Roger W. Lindsay ,  Michael A. Smith ,  Brett D. Lowe

IPC: H01L29/792 ,  H01L27/11582 ,  H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11524

CPC classification number: H01L27/11582 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11575

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures. Semiconductor device structures, semiconductor devices, and electronic systems are also described.

公开(公告)号：US20250098158A1

公开(公告)日：2025-03-20

申请号：US18966674

申请日：2024-12-03

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Brett D. Lowe

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L23/528 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure, slot structures vertically extending completely through the stack structure, and support pillar structures vertically extending through the stack structure. The stack structure comprises tiers vertically stacked relative to one another, each tier including a conductive material and insulative material vertically neighboring the conductive material. The stack structure includes a staircase structure therein comprising steps defined by edges of at least some of the tiers. The support pillar structures are arranged in rows horizontally extending in a first direction. The slot structures divide the stack structure into block structures. The microelectronic device further comprises additional slot structures within a horizontal area of one of the block structures. The additional slot structures include a first additional slot structure at least partially intersecting one of the rows of the support pillar structures. The additional slot structures also include a second additional slot structure horizontally spaced apart from the first additional slot structure and each of the rows of the support pillar structures in a second direction orthogonal to the first direction.

公开(公告)号：US20230157015A1

公开(公告)日：2023-05-18

申请号：US18152647

申请日：2023-01-10

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Brett D. Lowe

IPC: H10B41/27 ,  G11C5/06 ,  H01L23/528 ,  G11C5/02 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L23/528 ,  G11C5/025 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described.