公开(公告)号：US5452251A

公开(公告)日：1995-09-19

申请号：US79738

申请日：1993-06-22

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C11/40

CPC分类号： G11C29/80 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C2029/5004 ,  G11C29/88

摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

摘要翻译： 半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元 字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。 此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。 第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任一个有缺陷时，选择在2n个字线之外准备的2k个字线的块。 因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

公开(公告)号：US20070298784A1

公开(公告)日：2007-12-27

申请号：US11589506

申请日：2006-10-30

申请人： Minoru Yamashita ,  Takato Yokouchi ,  Tadatsugu Kotani ,  Kazuo Maehara ,  Yuji Fujimoto

发明人： Minoru Yamashita ,  Takato Yokouchi ,  Tadatsugu Kotani ,  Kazuo Maehara ,  Yuji Fujimoto

IPC分类号： H04Q7/20

CPC分类号： H04M1/236 ,  H04M1/0214 ,  H04M1/72522 ,  H04M1/72558 ,  H04M1/72583 ,  H04M2250/16 ,  H04M2250/52

摘要： According to an aspect of the invention, there is provided an information processing device including: a display unit configured to display a plurality of setting informations of a setting of function indicated by indication information displayed on a standby screen; a key unit configured to accept a selection of one piece of setting information among the plurality of setting informations; a control unit configured to cancel or change function setting, based on the setting information of which the selection is accepted by the key unit; and a display control unit configured to control a display of the indication information, which is performed by the display unit, in accordance with the cancel or the change of function setting performed by the control unit.

摘要翻译： 根据本发明的一个方面，提供了一种信息处理设备，包括：显示单元，被配置为显示由待机屏幕上显示的指示信息所指示的功能设置的多个设置信息; 键单元，被配置为接受所述多个设置信息中的一条设置信息的选择; 控制单元，被配置为基于所述选择被所述键单元接受的设置信息来取消或改变功能设置; 以及显示控制单元，被配置为根据由控制单元执行的功能设置的取消或改变来控制由显示单元执行的指示信息的显示。

公开(公告)号：US06934194B2

公开(公告)日：2005-08-23

申请号：US10631812

申请日：2003-08-01

申请人： Satoshi Takahashi ,  Minoru Yamashita

发明人： Satoshi Takahashi ,  Minoru Yamashita

IPC分类号： G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0475

摘要： A nonvolatile memory has a plurality of memory cells, each of the memory cells having a first and a second source/drain areas, a control gate, and an insulating trap layer disposed between the control gate and a channel area lying between the first and the second source/drain areas. The trap layer includes a use bit area in proximity to the first source/drain area, for storing data depending on the presence or absence of electric charge to be trapped, and a non-use bit area in proximity to the second source/drain area, in which the electric charge is trapped while data is held in the use bit area. Preferably, in the state where erasing operation is completed, the non-use bit area is brought into a state where electric charge is trapped therein.

摘要翻译： 非易失性存储器具有多个存储单元，每个存储单元具有第一和第二源极/漏极区域，控制栅极和绝缘陷阱层，其设置在控制栅极和位于第一和/ 第二源/漏区。 捕获层包括靠近第一源极/漏极区域的使用位区域，用于根据要被捕获的电荷的存在或不存在来存储数据，以及靠近第二源极/漏极区域的不使用位区域 ，其中在使用位区域中保持数据时电荷被捕获。 优选地，在擦除操作完成的状态下，不使用位区域进入电荷被捕获的状态。

公开(公告)号：US06914824B2

公开(公告)日：2005-07-05

申请号：US10392912

申请日：2003-03-21

申请人： Minoru Yamashita ,  Yuichi Einaga ,  Kazunari Kido

发明人： Minoru Yamashita ,  Yuichi Einaga ,  Kazunari Kido

IPC分类号： G11C16/06 ,  G11C16/02 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C16/0491 ,  G11C16/26

摘要： A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.

摘要翻译： 一种半导体存储器，可以防止在读取时间减少余量。 要读取的存储单元中的漏极与充电位线之间的浮置状态的位线在一定时间段内被充电。

公开(公告)号：US06807433B2

公开(公告)日：2004-10-19

申请号：US10098318

申请日：2002-03-18

申请人： Hisashi Oota ,  Kiyoshi Wagai ,  Minoru Yamashita

发明人： Hisashi Oota ,  Kiyoshi Wagai ,  Minoru Yamashita

IPC分类号： H04B138

CPC分类号： H04M1/0245 ,  H04M1/0214 ,  H04M1/22 ,  H04M1/575 ,  H04M1/72519 ,  H04M19/048

摘要： A mobile communication terminal is provided with a light-emitting element for notifying an unanswered incoming call. When the cancellation of an incoming call is canceled in a state where an incoming call response operation has not been carried out, the mobile communication terminal is brought into the standby state and then the light-emitting element is caused to emit light.

摘要翻译： 移动通信终端设置有用于通知未应答来电的发光元件。 当在没有进行来电响应操作的状态下取消来电时，移动通信终端进入待机状态，然后使发光元件发光。

公开(公告)号：US06765828B2

公开(公告)日：2004-07-20

申请号：US10356496

申请日：2003-02-03

申请人： Minoru Yamashita

发明人： Minoru Yamashita

IPC分类号： G11C1604

CPC分类号： G11C16/30 ,  G11C16/28

摘要： A non-volatile semiconductor storage device provided with a boost circuit for setting, for at least a certain period of time, a source line selectively connected to a memory cell to a negative potential, when reading out data from the memory cell is disclosed.

摘要翻译： 公开了一种非易失性半导体存储装置，其具有升压电路，用于在从存储单元读出数据时，将至少一定时间内选择性地连接到存储单元的源极线设置为负电位。

公开(公告)号：US5982670A

公开(公告)日：1999-11-09

申请号：US196441

申请日：1998-11-20

申请人： Minoru Yamashita

发明人： Minoru Yamashita

IPC分类号： G11C16/02 ,  G11C16/16 ,  G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/16

摘要： The present invention is a non-volatile memory device, wherein programming or erasing of memory cells is carried out by injecting or removing carriers in floating gates in the memory cells, comprising: a plurality of memory blocks each comprising a plurality of memory cells, respectively; and an erasing circuit for applying an erasing stress in units of the memory blocks and verifying that erasure has been completed in units of memory cells; wherein the erasing circuit applies an erasing stress to the plurality of memory blocks simultaneously until a past erasing stress minimum value for the plurality of memory blocks. According to the aforementioned invention, an erasing stress value, such as a number of erasing stress applications, is recorded for each memory block in past erasing operations, and the minimum erasing stress value of these erasing stress values is recorded. In the next erasing operation, an erasing stress is applied to a plurality of memory blocks in one batch, until this minimum erasing stress value is reached. Therefore, the erasing time can be shortened in comparison with a conventional method where application of erasing stress and erasure verification are repeated for each memory block, after respectively.

摘要翻译： 本发明是一种非易失性存储器件，其中存储器单元的编程或擦除通过在存储器单元中的浮动栅极中注入或去除载体来执行，包括：分别包括多个存储器单元的多个存储器块 ; 以及擦除电路，用于以存储块为单位施加擦除应力，并且以存储单元为单位验证擦除是否完成; 其中所述擦除电路同时向所述多个存储块施加擦除应力，直到所述多个存储块的过去的擦除应力最小值为止。 根据上述发明，在过去的擦除操作中，针对每个存储块记录擦除应力应用的数量等擦除应力值，并且记录这些擦除应力值的最小擦除应力值。 在下一个擦除操作中，一批中的擦除应力被施加到多个存储块，直到达到最小擦除应力值。 因此，与分别对每个存储块重复执行擦除应力和擦除验证的传统方法相比，可以缩短擦除时间。

公开(公告)号：US5870337A

公开(公告)日：1999-02-09

申请号：US986575

申请日：1997-12-05

申请人： Takao Akaogi ,  Yasushige Ogawa ,  Tatsuya Kajita ,  Hisayoshi Watanabe ,  Minoru Yamashita

发明人： Takao Akaogi ,  Yasushige Ogawa ,  Tatsuya Kajita ,  Hisayoshi Watanabe ,  Minoru Yamashita

IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C29/00 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  G11C16/06

CPC分类号： H01L27/11526 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C29/846 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11543

摘要： A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

摘要翻译： 闪存可擦除半导体存储器件具有存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制 电路提供写入控制信号时，写入信息。 写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。 此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。

公开(公告)号：US5761127A

公开(公告)日：1998-06-02

申请号：US978976

申请日：1992-11-20

申请人： Takao Akaogi ,  Yasushige Ogawa ,  Tatsuya Kajita ,  Hisayoshi Watanabe ,  Minoru Yamashita

发明人： Takao Akaogi ,  Yasushige Ogawa ,  Tatsuya Kajita ,  Hisayoshi Watanabe ,  Minoru Yamashita

IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C29/00 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  G11C16/06

CPC分类号： H01L27/11526 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C29/846 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11543

摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

公开(公告)号：US07835183B2

公开(公告)日：2010-11-16

申请号：US11986331

申请日：2007-11-20

申请人： Minoru Yamashita

发明人： Minoru Yamashita

IPC分类号： G11C16/04

CPC分类号： G11C16/28 ,  G11C16/3454 ,  G11C16/3459

摘要： A nonvolatile memory device that responds to a decrease in electric charge stored in memory cells attributed to the charge loss phenomenon occurring during program operation by adjusting the level of a program verify operation according to the degree of the charge loss so that the program operation can be performed with little (if any) interruption.

摘要翻译： 一种非易失性存储器件，其响应于由于在编程操作期间发生的电荷损失现象而存储在存储器单元中的电荷减少，通过根据电荷损失的程度调节程序验证操作的电平，使得程序操作可以 执行很少（如果有）中断。