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    Semiconductor memory device
    11.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06751154B2

    公开(公告)日：2004-06-15

    申请号：US10400043

    申请日：2003-03-26

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： G11C700

    CPC分类号： G11C7/222 ,  G11C7/1042 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/06 ,  G11C8/16 ,  G11C8/18 ,  G11C11/405 ,  G11C11/4076

    摘要： A semiconductor memory device includes: a memory cell configured with two transistors and one capacitor; two word drivers for controlling two word lines alternately, the two word lines controlling reading/writing with respect to the memory cell; two address latch circuits for latching a first address signal to select one of the word drivers, the two address latch circuits being respectively provided upstream from the two word drivers; and an address decoder for decoding a second address signal to generate the first address signal. In this device, the address decoder supplies the first address signal in common to both of the two address latch circuits.

    摘要翻译： 半导体存储器件包括：配置有两个晶体管和一个电容器的存储单元; 交替地控制两个字线的两个字驱动器，两个字线相对于存储器单元控制读/写; 两个地址锁存电路，用于锁存第一地址信号以选择一个字驱动器，两个地址锁存电路分别设置在两个字驱动器的上游; 以及地址解码器，用于解码第二地址信号以产生第一地址信号。 在该装置中，地址解码器将共同的第一地址信号提供给两个地址锁存电路。

    Semiconductor memory device
    12.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06751116B2

    公开(公告)日：2004-06-15

    申请号：US10233486

    申请日：2002-09-04

    申请人： Naoki Kuroda ,  Masashi Agata

    发明人： Naoki Kuroda ,  Masashi Agata

    IPC分类号： G11C1124

    CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/2281

    摘要： A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

    摘要翻译： 包括要访问的存储单元的第一晶体管，第一位线对，第一列选择开关和数据线对的路径的端口A与包括存储器单元的第二晶体管的路径的端口B交错 要被访问的第二位线对，第二列选择开关和数据线对在时钟的两个周期中。 读取放大器将从位线对传送的数据放大到数据线对，并在时钟的一个周期内将结果数据输出到输入/输出缓冲器。 输入/输出缓冲器在时钟的一个周期内将从读取放大器接收到的数据输出到外部。

    Semiconductor memory device
    13.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08817551B2

    公开(公告)日：2014-08-26

    申请号：US13620667

    申请日：2012-09-14

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： G11C7/00 ,  G11C11/419 ,  G11C11/412

    CPC分类号： G11C11/412 ,  G11C7/14 ,  G11C11/419 ,  G11C29/023 ,  G11C29/026 ,  G11C29/24

    摘要： A semiconductor memory device includes a memory cell array block including a plurality of memory cells each including a data holding circuit configured to store data using a first and a second circuit elements and a transistor configured to connect the data holding circuit and a bit line together, sense amplifiers connected to bit lines directly or via switches, and a dummy memory cell array including a plurality of dummy memory cells each having the same circuit configuration as that of the memory cell with respect to the element size and the layout configuration. The plurality of dummy memory cells each include at least one inverter circuit configuration, and are connected together by the inverter circuits being connected together in series. An output signal of the inverter circuit of one in the final stage of the dummy memory cells is an activation signal for the sense amplifiers.

    摘要翻译： 半导体存储器件包括存储单元阵列块，其包括多个存储单元，每个存储单元包括数据保持电路，该数据保持电路被配置为使用第一和第二电路元件存储数据;以及晶体管，被配置为将数据保持电路和位线连接在一起， 直接或通过开关连接到位线的感测放大器，以及包括多个虚拟存储单元的虚拟存储单元阵列，每个虚拟存储单元具有与存储单元的元件尺寸和布局配置相同的电路配置。 多个虚拟存储单元各自包括至少一个反相器电路结构，并且通过串联连接在一起的反相器电路连接在一起。 虚拟存储单元的最后级中的一个的反相器电路的输出信号是用于读出放大器的激活信号。

    SEMICONDUCTOR MEMORY DEVICE
    15.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20110051489A1

    公开(公告)日：2011-03-03

    申请号：US12942627

    申请日：2010-11-09

    申请人： Naoki Kuroda ,  Yoshinobu Yamagami

    发明人： Naoki Kuroda ,  Yoshinobu Yamagami

    IPC分类号： G11C5/06

    CPC分类号： G11C11/412 ,  G11C8/16

    摘要： A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to connect the input of the first inverter and a write bit line, a read MOS transistor having a gate connected to the output of the first inverter, and a MOS switch configured to connect the read MOS transistor to a read bit line. The first and second inverters have different sizes and are connected to different source power supplies.

    摘要翻译： 半导体存储器件包括第一反相器和第二反相器，每个具有输入和输出，第一和第二反相器的每一个的输出连接到另一个的输入，以便存储数据; CMOS开关，被配置为连接 第一反相器的输入和写入位线，具有连接到第一反相器的输出的栅极的读取MOS晶体管和被配置为将读取的MOS晶体管连接到读取位线的MOS开关。 第一和第二逆变器具有不同的尺寸并连接到不同的源电源。

    Semiconductor integrated circuit
    16.
    发明申请
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US20070253125A1

    公开(公告)日：2007-11-01

    申请号：US11730683

    申请日：2007-04-03

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： H02H7/00

    CPC分类号： G11C29/12 ,  G11C5/147 ,  G11C29/12005 ,  G11C29/1201

    摘要： A semiconductor integrated circuit including on a single chip a plurality of circuit blocks and a plurality of internal power supply circuits for delivering a common supply voltage to the plurality of circuit blocks includes: a shared power supply interconnection for connecting the plurality of circuit blocks and the plurality of internal power supply circuits; and an external pad connected to the shared power supply interconnection. Whether or not each of the internal power supply circuits delivers the supply voltage is controlled by a certain power supply control signal.

    摘要翻译： 包括在单个芯片上的多个电路块的半导体集成电路和用于向多个电路块传送公共电源电压的多个内部电源电路包括：用于连接多个电路块的共享电源互连和 多个内部电源电路; 以及连接到共享电源互连的外部焊盘。 每个内部电源电路的输出电源电压是否由一定的电源控制信号控制。

    Semiconductor memory device
    17.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US07031199B2

    公开(公告)日：2006-04-18

    申请号：US10815709

    申请日：2004-04-02

    申请人： Naoki Kuroda ,  Masashi Agata

    发明人： Naoki Kuroda ,  Masashi Agata

    IPC分类号： G11C11/34

    CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/2281

    摘要： A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

    Semiconductor memory device and test method thereof
    18.
    发明授权
    Semiconductor memory device and test method thereof 失效
    半导体存储器件及其测试方法

    公开(公告)号：US06909624B2

    公开(公告)日：2005-06-21

    申请号：US10624890

    申请日：2003-07-23

    申请人： Hiroyuki Sadakata ,  Naoki Kuroda

    发明人： Hiroyuki Sadakata ,  Naoki Kuroda

    IPC分类号： G01R31/28 ,  G11C29/26 ,  G11C29/34 ,  G11C5/06

    CPC分类号： G11C29/56004 ,  G11C29/26 ,  G11C2029/0401 ,  G11C2029/1806 ,  G11C2029/2602

    摘要： In recent system LSIs, a plurality of RAMs differing in capacity and in bit width have come to be mounted on a single chip according to the needs on the system side. However, when testing the plurality of RAMs, if the RAMs differ in capacity, they cannot be tested using the same test pattern (for example, HALF-MARCH) even if a special pin is provided for each RAM, because X, Y address mapping differs between the different RAMs; accordingly, the test has to be performed by dividing the RAMs into groups each consisting of RAMs having the same memory space, and this has lead to increased test time. An external address signal and a test-only address signal are provided as RAM control signals and, in the latter case, the number of X, Y addresses in each of the RAMs 4 and 5 is set equal to that of the largest capacity RAM 3 within the same chip, thereby making the X, Y address mapping the same for all the RAMs 3 to 5.

    摘要翻译： 在近来的系统LSI中，根据系统侧的需要，将单个芯片上的容量和位宽不同的多个RAM进行安装。 然而，当测试多个RAM时，如果RAM的容量不同，即使为每个RAM提供特殊引脚，也不能使用相同的测试模式（例如，HALF-MARCH）进行测试，因为X，Y地址映射 不同的RAM之间有所不同; 因此，必须通过将RAM分成由具有相同存储空间的RAM组成的组来执行测试，并且这导致增加的测试时间。 提供外部地址信号和仅测试地址信号作为RAM控制信号，并且在后一种情况下，每个RAM4和5中的X，Y地址的数量被设置为等于最大容量RAM 3的数量 在同一个芯片内，从而使X，Y地址映射对于所有RAM3至5都是相同的。

    Power control for a plurality of internal power supply circuits of a semiconductor integrated circuit
    20.
    发明授权
    Power control for a plurality of internal power supply circuits of a semiconductor integrated circuit 有权
    用于半导体集成电路的多个内部电源电路的功率控制

    公开(公告)号：US07779277B2

    公开(公告)日：2010-08-17

    申请号：US11730683

    申请日：2007-04-03

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： G06F1/00 ,  G11C29/00 ,  H02J1/00

    CPC分类号： G11C29/12 ,  G11C5/147 ,  G11C29/12005 ,  G11C29/1201

    摘要： A semiconductor integrated circuit including on a single chip a plurality of circuit blocks and a plurality of internal power supply circuits for delivering a common supply voltage to the plurality of circuit blocks includes: a shared power supply interconnection for connecting the plurality of circuit blocks and the plurality of internal power supply circuits; and an external pad connected to the shared power supply interconnection. Whether or not each of the internal power supply circuits delivers the supply voltage is controlled by a certain power supply control signal.

    摘要翻译： 包括在单个芯片上的多个电路块的半导体集成电路和用于向多个电路块传送公共电源电压的多个内部电源电路包括：用于连接多个电路块的共享电源互连和 多个内部电源电路; 以及连接到共享电源互连的外部焊盘。 每个内部电源电路的输出电源电压是否由一定的电源控制信号控制。