公开(公告)号：US20120015113A1

公开(公告)日：2012-01-19

申请号：US12835574

申请日：2010-07-13

申请人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Shankar Venkataraman

发明人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Shankar Venkataraman

IPC分类号： C23C16/513

CPC分类号： C23C16/513 ,  C23C16/401 ,  C23C16/44

摘要： A method for forming a multi-layer silicon oxide film on a substrate includes performing a deposition cycle that comprises depositing a silicon oxide layer using a thermal chemical vapor deposition (CVD) process and depositing a silicon oxide layer using a plasma enhanced chemical vapor deposition (PECVD) process. The deposition cycle is repeated a specified number of times to form the multi-layer silicon oxide film comprising a plurality of silicon oxide layers formed using the thermal CVD process and a plurality of silicon oxide layers formed using the PECVD process. Each silicon oxide layer formed using the thermal CVD process is adjacent to at least one silicon oxide layer formed using the PECVD process.

摘要翻译： 在衬底上形成多层氧化硅膜的方法包括执行沉积循环，其包括使用热化学气相沉积（CVD）工艺沉积氧化硅层，并使用等离子体增强化学气相沉积法沉积氧化硅层（ PECVD）过程。 沉积循环重复规定次数以形成包含使用热CVD工艺形成的多个氧化硅层和使用PECVD工艺形成的多个氧化硅层的多层氧化硅膜。 使用热CVD工艺形成的每个氧化硅层与使用PECVD工艺形成的至少一个氧化硅层相邻。

公开(公告)号：US20110223760A1

公开(公告)日：2011-09-15

申请号：US13035034

申请日：2011-02-25

申请人： Zhong Qiang Hua ,  Manuel A. Hernandez ,  Lei Luo ,  Kedar Sapre

发明人： Zhong Qiang Hua ,  Manuel A. Hernandez ,  Lei Luo ,  Kedar Sapre

IPC分类号： H01L21/768

CPC分类号： H01L21/76898

摘要： A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 μm from a top surface of the nitride layer and an opening of less than about 10 μm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.

摘要翻译： 在半导体衬底中的通孔侧壁改善氧化物层的保形性的方法包括在半导体衬底的上表面上形成氮化物层，并形成延伸穿过氮化物层并进入半导体衬底的通孔。 通孔可以具有距离氮化物层的顶表面至少约50μm的深度和在氮化物层的顶表面处的小于约10μm的开口。 该方法还包括在氮化物层上并沿着通孔的侧壁和底部形成氧化物层。 可以在小于约450℃的温度下使用热化学气相沉积（CVD）工艺形成氧化物层，其中通孔底部的氧化物层的厚度为厚度的至少约50％ 在氮化物层的顶表面处的氧化物层。

公开(公告)号：US20100006032A1

公开(公告)日：2010-01-14

申请号：US12501195

申请日：2009-07-10

申请人： Kimberly Hinckley ,  Yizhen Zhang ,  Manuel A. Hernandez ,  Won B. Bang ,  Dmitry Lubomirsky

发明人： Kimberly Hinckley ,  Yizhen Zhang ,  Manuel A. Hernandez ,  Won B. Bang ,  Dmitry Lubomirsky

IPC分类号： C23C16/00

CPC分类号： C23C16/452 ,  C23C16/4481 ,  C23C16/45512 ,  C23C16/45591

摘要： Apparatus for use with a processing chamber are provided. In one aspect a blocker plate is provided including an annular plate having an inner portion of a first thickness and the annular plate having an aperture pattern including a center portion, a first patterned portion concentrically disposed around the center portion and comprising a first plurality of apertures having a first number of apertures, an second patterned portion concentrically disposed around the first patterned portion and comprising a second plurality of apertures having a second number of apertures greater than the first number of apertures, a perimeter portion concentrically disposed around the second patterned portion, and an outer portion comprising a raised concentric portion disposed on a perimeter of the annular plate. In another aspect, a second, third, and fourth blocker plates are provided. Additionally, a mixing apparatus and a liquid evaporating apparatus for use in a processing chamber are provided.

摘要翻译： 提供了一种用于处理室的设备。 在一个方面，提供了阻挡板，其包括具有第一厚度的内部部分的环形板，并且环形板具有包括中心部分的孔图案，第一图案化部分同心地设置在中心部分周围，并且包括第一多个孔 具有第一数量的孔，第二图案部分同心地设置在第一图案化部分周围，并且包括第二多个孔，其具有大于第一数量孔的第二数量的孔，围绕第二图案化部分同心设置的周边部分， 以及包括设置在所述环形板的周边上的升高的同心部分的外部部分。 另一方面，提供第二，第三和第四阻滞板。 此外，提供了一种用于处理室的混合装置和液体蒸发装置。

公开(公告)号：US20120058281A1

公开(公告)日：2012-03-08

申请号：US13041201

申请日：2011-03-04

申请人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Zhitao Cao ,  Kedar Sapre ,  Ajay Bhatnagar

发明人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Zhitao Cao ,  Kedar Sapre ,  Ajay Bhatnagar

IPC分类号： B05D5/00 ,  C23C16/56 ,  C23C16/50 ,  C23C16/40 ,  C23C16/44

CPC分类号： H01L21/02164 ,  C23C16/40 ,  C23C16/56 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02362

摘要： A method for forming a pre-metal dielectric (PMD) layer or an inter-metal dielectric (IMD) layer over a substrate includes placing the substrate in a chemical vapor deposition (CVD) process chamber and forming a first oxide layer over the substrate in the CVD process chamber. The first oxide layer is formed using a thermal CVD process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The method also includes forming a second oxide layer over the first oxide layer in the CVD process chamber. The second oxide layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The substrate remains in the CVD process chamber during formation of the first oxide layer and the second oxide layer.

摘要翻译： 在衬底上形成预金属电介质（PMD）层或金属间电介质（IMD）层的方法包括将衬底放置在化学气相沉积（CVD）处理室中，并在衬底上形成第一氧化物层 CVD处理室。 第一氧化物层使用热CVD工艺在约450℃或更低的温度和低于大气压的压力下形成。 该方法还包括在CVD处理室中的第一氧化物层上形成第二氧化物层。 使用等离子体增强化学气相沉积（PECVD）工艺在约450℃或更低的温度和低于大气压的压力下形成第二氧化物层。 在形成第一氧化物层和第二氧化物层期间，衬底保留在CVD处理室中。

公开(公告)号：US20110129990A1

公开(公告)日：2011-06-02

申请号：US12843726

申请日：2010-07-26

申请人： Tushar V. Mandrekar ,  Shankar Venkataraman ,  Zhong Qiang Hua ,  Manuel A. Hernandez

发明人： Tushar V. Mandrekar ,  Shankar Venkataraman ,  Zhong Qiang Hua ,  Manuel A. Hernandez

IPC分类号： H01L21/22

CPC分类号： H01L21/2256 ,  H01L29/66803

摘要： Methods for doping a non-planar structure by forming a conformal doped silicon glass layer on the non-planar structure are disclosed. A substrate having the non-planar structure formed thereon is positioned in chemical vapor deposition process chamber to deposit a conformal SACVD layer of doped glass (e.g. BSG or PSG). The substrate is then exposed to RTP or laser anneal step to diffuse the dopant into the non-planar structure and the doped glass layer is then removed by etching.

摘要翻译： 公开了通过在非平面结构上形成共形掺杂的硅玻璃层来掺杂非平面结构的方法。 将其上形成有非平面结构的基板放置在化学气相沉积处理室中以沉积掺杂玻璃（例如BSG或PSG）的共形SACVD层。 然后将衬底暴露于RTP或激光退火步骤以将掺杂剂扩散到非平面结构中，然后通过蚀刻去除掺杂的玻璃层。

公开(公告)号：US20100159711A1

公开(公告)日：2010-06-24

申请号：US12489234

申请日：2009-06-22

申请人： Shankar Venkataraman ,  Hiroshi Hamana ,  Manuel A. Hernandez ,  Nitin K. Ingle ,  Paul Edward Gee

发明人： Shankar Venkataraman ,  Hiroshi Hamana ,  Manuel A. Hernandez ,  Nitin K. Ingle ,  Paul Edward Gee

IPC分类号： H01L21/31 ,  H01L21/762

CPC分类号： H01L21/31612 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/76224

摘要： Methods of depositing silicon oxide layers on substrates involve flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that a uniform silicon oxide growth rate is achieved across the substrate surface. The surface of silicon oxide layers grown according to embodiments may have a reduced roughness when grown with the additive precursor. In other aspects of the disclosure, silicon oxide layers are deposited on a patterned substrate with trenches on the surface by flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that the trenches are filled with a reduced quantity and/or size of voids within the silicon oxide filler material.

摘要翻译： 在衬底上沉积氧化硅层的方法包括使含硅前体，氧化气体，水和添加剂前体流入处理室，使得在衬底表面上实现均匀的氧化硅生长速率。 根据实施例生长的氧化硅层的表面可以在与添加剂前体一起生长时具有减小的粗糙度。 在本公开的其他方面中，通过使含硅前体，氧化气体，水和添加剂前体流入处理室，将硅氧化物层沉积在具有表面上的沟槽的图案化衬底上，使得沟槽填充有 氧化硅填充材料内的空隙的数量和/或尺寸减小。

公开(公告)号：US07161767B2

公开(公告)日：2007-01-09

申请号：US10195471

申请日：2002-07-16

申请人： Manuel A. Hernandez ,  Yen Fu

发明人： Manuel A. Hernandez ,  Yen Fu

IPC分类号： G11B5/48 ,  G11B21/21

CPC分类号： G11B5/486

摘要： Methods and devices are described that provide improved electromagnetic interference (EMI) protection for suspension assemblies. In one embodiment, a ground line is provided among the traces that are used in the suspension. Alternatively, a top ground plane is provided on top of the conductive traces with an interposed insulative layer. The ground line and/or the top ground plane provide EMI protection for read and write signals traveling through the traces (e.g., read and write traces) of the suspension assembly. The ground line and/or the top ground plane reduce the interaction between the read and the write traces, thus minimizing cross talk.

摘要翻译： 描述了为悬架组件提供改进的电磁干扰（EMI）保护的方法和装置。 在一个实施例中，在悬架中使用的迹线之间提供接地线。 或者，顶部接地平面设置在导电迹线的顶部，并具有插入的绝缘层。 接地线和/或顶部接地平面为通过悬挂组件的迹线（例如，读取和写入迹线）传输的读取和写入信号提供EMI保护。 接地线和/或顶部接地平面减小读取和写入轨迹之间的相互作用，从而最小化串扰。

公开(公告)号：US07092214B2

公开(公告)日：2006-08-15

申请号：US10229591

申请日：2002-08-27

申请人： Manuel A. Hernandez

发明人： Manuel A. Hernandez

IPC分类号： G11B5/48

CPC分类号： H05K1/028 ,  G11B5/486 ,  H05K1/0266 ,  H05K2201/09145 ,  H05K2201/09936

摘要： A wireless suspension design is described that can be used in varying types of drive designs. In one embodiment, a flex circuit is provided with at least two indicia to indicate where the flex circuit is to be bent when attaching it to a head stack assembly.