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    Method for doping non-planar transistors
    1.
    发明授权
    Method for doping non-planar transistors 失效
    掺杂非平面晶体管的方法

    公开(公告)号：US08114761B2

    公开(公告)日：2012-02-14

    申请号：US12843726

    申请日：2010-07-26

    申请人： Tushar V. Mandrekar ,  Shankar Venkataraman ,  Zhong Qiang Hua ,  Manuel A. Hernandez

    发明人： Tushar V. Mandrekar ,  Shankar Venkataraman ,  Zhong Qiang Hua ,  Manuel A. Hernandez

    IPC分类号： H01L21/00

    CPC分类号： H01L21/2256 ,  H01L29/66803

    摘要： Methods for doping a non-planar structure by forming a conformal doped silicon glass layer on the non-planar structure are disclosed. A substrate having the non-planar structure formed thereon is positioned in chemical vapor deposition process chamber to deposit a conformal SACVD layer of doped glass (e.g. BSG or PSG). The substrate is then exposed to RTP or laser anneal step to diffuse the dopant into the non-planar structure and the doped glass layer is then removed by etching.

    摘要翻译： 公开了通过在非平面结构上形成共形掺杂的硅玻璃层来掺杂非平面结构的方法。 将其上形成有非平面结构的基板放置在化学气相沉积处理室中以沉积掺杂玻璃（例如BSG或PSG）的共形SACVD层。 然后将衬底暴露于RTP或激光退火步骤以将掺杂剂扩散到非平面结构中，然后通过蚀刻去除掺杂的玻璃层。

    METHOD FOR DOPING NON-PLANAR TRANSISTORS
    2.
    发明申请
    METHOD FOR DOPING NON-PLANAR TRANSISTORS 失效
    非平面晶体管的方法

    公开(公告)号：US20110129990A1

    公开(公告)日：2011-06-02

    申请号：US12843726

    申请日：2010-07-26

    申请人： Tushar V. Mandrekar ,  Shankar Venkataraman ,  Zhong Qiang Hua ,  Manuel A. Hernandez

    发明人： Tushar V. Mandrekar ,  Shankar Venkataraman ,  Zhong Qiang Hua ,  Manuel A. Hernandez

    IPC分类号： H01L21/22

    CPC分类号： H01L21/2256 ,  H01L29/66803

    摘要： Methods for doping a non-planar structure by forming a conformal doped silicon glass layer on the non-planar structure are disclosed. A substrate having the non-planar structure formed thereon is positioned in chemical vapor deposition process chamber to deposit a conformal SACVD layer of doped glass (e.g. BSG or PSG). The substrate is then exposed to RTP or laser anneal step to diffuse the dopant into the non-planar structure and the doped glass layer is then removed by etching.

    摘要翻译： 公开了通过在非平面结构上形成共形掺杂的硅玻璃层来掺杂非平面结构的方法。 将其上形成有非平面结构的基板放置在化学气相沉积处理室中以沉积掺杂玻璃（例如BSG或PSG）的共形SACVD层。 然后将衬底暴露于RTP或激光退火步骤以将掺杂剂扩散到非平面结构中，然后通过蚀刻去除掺杂的玻璃层。

    METHODS FOR FORMING LOW STRESS DIELECTRIC FILMS
    3.
    发明申请
    METHODS FOR FORMING LOW STRESS DIELECTRIC FILMS 审中-公开
    形成低应力电介质膜的方法

    公开(公告)号：US20120015113A1

    公开(公告)日：2012-01-19

    申请号：US12835574

    申请日：2010-07-13

    申请人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Shankar Venkataraman

    发明人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Shankar Venkataraman

    IPC分类号： C23C16/513

    CPC分类号： C23C16/513 ,  C23C16/401 ,  C23C16/44

    摘要： A method for forming a multi-layer silicon oxide film on a substrate includes performing a deposition cycle that comprises depositing a silicon oxide layer using a thermal chemical vapor deposition (CVD) process and depositing a silicon oxide layer using a plasma enhanced chemical vapor deposition (PECVD) process. The deposition cycle is repeated a specified number of times to form the multi-layer silicon oxide film comprising a plurality of silicon oxide layers formed using the thermal CVD process and a plurality of silicon oxide layers formed using the PECVD process. Each silicon oxide layer formed using the thermal CVD process is adjacent to at least one silicon oxide layer formed using the PECVD process.

    摘要翻译： 在衬底上形成多层氧化硅膜的方法包括执行沉积循环，其包括使用热化学气相沉积（CVD）工艺沉积氧化硅层，并使用等离子体增强化学气相沉积法沉积氧化硅层（ PECVD）过程。 沉积循环重复规定次数以形成包含使用热CVD工艺形成的多个氧化硅层和使用PECVD工艺形成的多个氧化硅层的多层氧化硅膜。 使用热CVD工艺形成的每个氧化硅层与使用PECVD工艺形成的至少一个氧化硅层相邻。

    METHODS FOR FORMING LOW MOISTURE DIELECTRIC FILMS
    4.
    发明申请
    METHODS FOR FORMING LOW MOISTURE DIELECTRIC FILMS 审中-公开
    形成低水分电介质膜的方法

    公开(公告)号：US20120058281A1

    公开(公告)日：2012-03-08

    申请号：US13041201

    申请日：2011-03-04

    申请人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Zhitao Cao ,  Kedar Sapre ,  Ajay Bhatnagar

    发明人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Zhitao Cao ,  Kedar Sapre ,  Ajay Bhatnagar

    IPC分类号： B05D5/00 ,  C23C16/56 ,  C23C16/50 ,  C23C16/40 ,  C23C16/44

    CPC分类号： H01L21/02164 ,  C23C16/40 ,  C23C16/56 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02362

    摘要： A method for forming a pre-metal dielectric (PMD) layer or an inter-metal dielectric (IMD) layer over a substrate includes placing the substrate in a chemical vapor deposition (CVD) process chamber and forming a first oxide layer over the substrate in the CVD process chamber. The first oxide layer is formed using a thermal CVD process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The method also includes forming a second oxide layer over the first oxide layer in the CVD process chamber. The second oxide layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The substrate remains in the CVD process chamber during formation of the first oxide layer and the second oxide layer.

    摘要翻译： 在衬底上形成预金属电介质（PMD）层或金属间电介质（IMD）层的方法包括将衬底放置在化学气相沉积（CVD）处理室中，并在衬底上形成第一氧化物层 CVD处理室。 第一氧化物层使用热CVD工艺在约450℃或更低的温度和低于大气压的压力下形成。 该方法还包括在CVD处理室中的第一氧化物层上形成第二氧化物层。 使用等离子体增强化学气相沉积（PECVD）工艺在约450℃或更低的温度和低于大气压的压力下形成第二氧化物层。 在形成第一氧化物层和第二氧化物层期间，衬底保留在CVD处理室中。

    Conformality of oxide layers along sidewalls of deep vias
    5.
    发明授权
    Conformality of oxide layers along sidewalls of deep vias 有权
    深层通孔侧壁氧化层的一致性

    公开(公告)号：US08404583B2

    公开(公告)日：2013-03-26

    申请号：US13035034

    申请日：2011-02-25

    申请人： Zhong Qiang Hua ,  Manuel A. Hernandez ,  Lei Luo ,  Kedar Sapre

    发明人： Zhong Qiang Hua ,  Manuel A. Hernandez ,  Lei Luo ,  Kedar Sapre

    IPC分类号： H01L21/44 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/76898

    摘要： A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 μm from a top surface of the nitride layer and an opening of less than about 10 μm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.

    摘要翻译： 在半导体衬底中的通孔侧壁改善氧化物层的保形性的方法包括在半导体衬底的上表面上形成氮化物层，并形成延伸穿过氮化物层并进入半导体衬底的通孔。 通孔可以具有距离氮化物层的顶表面至少约50μm的深度和在氮化物层的顶表面处的小于约10μm的开口。 该方法还包括在氮化物层上并沿着通孔的侧壁和底部形成氧化物层。 可以在小于约450℃的温度下使用热化学气相沉积（CVD）工艺形成氧化物层，其中通孔底部的氧化物层的厚度为厚度的至少约50％ 在氮化物层的顶表面处的氧化物层。

    CONFORMALITY OF OXIDE LAYERS ALONG SIDEWALLS OF DEEP VIAS
    6.
    发明申请
    CONFORMALITY OF OXIDE LAYERS ALONG SIDEWALLS OF DEEP VIAS 有权
    深层六角形氧化层的一致性

    公开(公告)号：US20110223760A1

    公开(公告)日：2011-09-15

    申请号：US13035034

    申请日：2011-02-25

    申请人： Zhong Qiang Hua ,  Manuel A. Hernandez ,  Lei Luo ,  Kedar Sapre

    发明人： Zhong Qiang Hua ,  Manuel A. Hernandez ,  Lei Luo ,  Kedar Sapre

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76898

    摘要： A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 μm from a top surface of the nitride layer and an opening of less than about 10 μm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.

    摘要翻译： 在半导体衬底中的通孔侧壁改善氧化物层的保形性的方法包括在半导体衬底的上表面上形成氮化物层，并形成延伸穿过氮化物层并进入半导体衬底的通孔。 通孔可以具有距离氮化物层的顶表面至少约50μm的深度和在氮化物层的顶表面处的小于约10μm的开口。 该方法还包括在氮化物层上并沿着通孔的侧壁和底部形成氧化物层。 可以在小于约450℃的温度下使用热化学气相沉积（CVD）工艺形成氧化物层，其中通孔底部的氧化物层的厚度为厚度的至少约50％ 在氮化物层的顶表面处的氧化物层。

    MULTI-STEP DEP-ETCH-DEP HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESSES FOR DIELECTRIC GAPFILLS
    8.
    发明申请
    MULTI-STEP DEP-ETCH-DEP HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESSES FOR DIELECTRIC GAPFILLS 审中-公开
    多级DEP-ETCH-DEP高密度等离子体化学气相沉积工艺用于电介质

    公开(公告)号：US20080142483A1

    公开(公告)日：2008-06-19

    申请号：US11947619

    申请日：2007-11-29

    申请人： Zhong Qiang Hua ,  Rionard Purnawan ,  Jason Thomas Bloking ,  Anchuan Wang ,  Young S. Lee ,  Ellie Y. Yieh

    发明人： Zhong Qiang Hua ,  Rionard Purnawan ,  Jason Thomas Bloking ,  Anchuan Wang ,  Young S. Lee ,  Ellie Y. Yieh

    IPC分类号： B44C1/22

    CPC分类号： C23C16/401 ,  C23C16/045 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/3145 ,  H01L21/31612

    摘要： A method of forming a dielectric material in a substrate gap using a high-density plasma is described. The method may include depositing a first portion of the dielectric material into the gap with the high-density plasma. The deposition may form a protruding structure that at least partially blocks the deposition of the dielectric material into the gap. The first portion of dielectric material is exposed to an etchant that includes reactive species from a mixture that includes NH3 and NF3. The etchant forms a solid reaction product with the protruding structure, and the solid reaction product may be removed from the substrate. A final portion of the dielectric material may be deposited in the gap with the high-density plasma.

    摘要翻译： 描述了使用高密度等离子体在衬底间隙中形成电介质材料的方法。 该方法可以包括将电介质材料的第一部分沉积到具有高密度等离子体的间隙中。 沉积可以形成至少部分地阻挡介电材料沉积到间隙中的突出结构。 电介质材料的第一部分暴露于包括来自包括NH 3和N N 3 3的混合物的反应物质的蚀刻剂。 蚀刻剂形成具有突出结构的固体反应产物，并且固体反应产物可以从基底上除去。 介电材料的最终部分可以与高密度等离子体在间隙中沉积。