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    Method of making a DRAM cell with trench capacitor
    13.
    发明授权
    Method of making a DRAM cell with trench capacitor 失效
    制造具有沟槽电容器的DRAM单元的方法

    公开(公告)号：US5395786A

    公开(公告)日：1995-03-07

    申请号：US269852

    申请日：1994-06-30

    申请人： Louis L. Hsu ,  Sieki Ogura ,  Joseph F. Shepard

    发明人： Louis L. Hsu ,  Sieki Ogura ,  Joseph F. Shepard

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10861

    摘要： A DRAM cell of the trench capacitor type is formed by a simplified process that reduces cost and increases process latitude by forming the trench collar in a single step of expanding a shallow trench horizontally and conformally coating the collar; etching the trench to its final depth and implanting the bottom heavily and doping the walls lightly; recessing the poly liner in a non-critical step that exposes a contact area between the top of the poly and the adjacent transistor electrode.

    摘要翻译： 沟槽电容器类型的DRAM单元通过简化的工艺形成，该工艺通过在使水平并且适形地涂覆套环的单个步骤中形成沟槽套圈来降低成本并增加工艺的纬度; 将沟槽蚀刻到其最终深度并且重要地注入底部并轻轻掺杂壁; 在暴露多晶硅和相邻晶体管电极的顶部之间的接触面积的非关键步骤中使多层衬垫凹陷。

    Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding
    14.
    发明授权
    Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding 失效
    半导体器件和晶片结构通过晶片接合具有平面埋入互连

    公开(公告)号：US5382832A

    公开(公告)日：1995-01-17

    申请号：US131344

    申请日：1993-10-04

    申请人： Taqi N. Buti ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Joseph F. Shepard

    发明人： Taqi N. Buti ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Joseph F. Shepard

    IPC分类号： H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L23/48 ,  H01L27/01

    CPC分类号： H01L25/50 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L2924/0002 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S438/977

    摘要： A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate having an oxide layer thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

    摘要翻译： 公开了一种适于在其上形成半导体器件的晶片结构，并且具有用于根据预定互连图案互连所需半导体器件的掩埋互连结构及其制造方法。 晶片结构包括具有适于形成期望的半导体器件的第一厚度的初级衬底。 主衬底还包括：a）根据预定互连图案形成在初级衬底的底表面上的第二厚度的导电互连衬垫，b）形成在第一衬底的底表面上的第三厚度的第一隔离衬垫 导电互连焊盘，以及c）形成在与主基板相对的互连焊盘的表面上的第四厚度的互连焊盘盖，其中互连焊盘帽包括适于晶片接合的材料，并且其中第二厚度 厚度和第四厚度等于第三厚度。 该结构还包括其上结合有互连衬垫帽和主晶片的第一隔离垫的氧化物层的二次衬底。

    Formation of bit lines for ram device
    17.
    发明授权
    Formation of bit lines for ram device 失效
    形成柱塞装置的位线

    公开(公告)号：US4403394A

    公开(公告)日：1983-09-13

    申请号：US217371

    申请日：1980-12-17

    申请人： Joseph F. Shepard ,  Paul J. Tsang

    发明人： Joseph F. Shepard ,  Paul J. Tsang

    IPC分类号： H01L27/10 ,  H01L21/28 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/532 ,  H01L27/108 ,  H01L29/78 ,  H01L21/22

    CPC分类号： H01L21/76889 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S438/98

    摘要： A conductor bit line for a dynamic random access memory (RAM) structure is formed of a material selected from the group consisting of polycrystalline silicon and a metal silicide, polycrystalline silicon and a conductive metal, and polycrystalline silicon, a metal silicide, and a conductive metal with the polycrystalline silicon contacting at least a portion of the drain region of the field effect transistor of each of a plurality of cells of the RAM structure via a self-aligned contact. When the selected material is polycrystalline silicon and a metal silicide, the conductor bit line is continuous. When the selected material is polycrystalline silicon and a conductive metal or polycrystalline silicon, a metal silicide, and a conductive metal, the polycrystalline silicon contacts with each of the drain regions while the conductive metal connects the polycrystalline silicon overlying adjacent drain regions when the selected material is polycrystalline silicon and a conductive metal and connects the metal silicide on the polycrystalline silicon overlying adjacent drain regions when the selected material is polycrystalline silicon, a metal silicide, and a conductive metal.

    摘要翻译： 用于动态随机存取存储器（RAM）结构的导体位线由选自多晶硅和金属硅化物，多晶硅和导电金属的组中的材料形成，多晶硅，金属硅化物和导电 金属与多晶硅经由自对准接触接触RAM结构的多个单元中的每一个的场效应晶体管的漏极区域的至少一部分。 当所选择的材料是多晶硅和金属硅化物时，导体位线是连续的。 当所选择的材料是多晶硅和导电金属或多晶硅，金属硅化物和导电金属时，多晶硅与每个漏极区接触，而当所选材料的导电金属连接覆盖相邻漏极区的多晶硅时 是多晶硅和导电金属，并且当所选择的材料是多晶硅，金属硅化物和导电金属时，将覆盖在相邻漏极区域上的多晶硅上的金属硅化物连接。

    Shallow trench isolation with self aligned PSG layer
    18.
    发明授权
    Shallow trench isolation with self aligned PSG layer 失效
    浅沟槽隔离与自对准PSG层

    公开(公告)号：US5729043A

    公开(公告)日：1998-03-17

    申请号：US729559

    申请日：1996-10-11

    申请人： Joseph F. Shepard

    发明人： Joseph F. Shepard

    IPC分类号： H01L21/762 ,  H01L29/76 ,  H01L23/58 ,  H01L29/00

    CPC分类号： H01L21/76237

    摘要： A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO.sub.2 plugs is proposed. The SiO.sub.2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench formation to tie up any sodium ionic contamination from processes prior to gate formation. P impurity layer is formed below the surface of the deposited SiO.sub.2 layer. A preferred method for forming the buried P layer is by shallow implantation in a vertical direction into the deposited SiO.sub.2 layer prior to planarization. The process is self aligned to the trench isolation regions.

    摘要翻译： 提出了一种用于形成沟槽隔离和使用SiO2插塞的特定浅沟槽隔离（STI）的方法。 STI的SiO 2塞具有在沟槽形成期间和之后引入的富含磷（P）的掩埋层，以在栅极形成之前将工艺中的任何钠离子污染物结合起来。 在沉积的SiO 2层的表面下方形成P杂质层。 用于形成掩埋P层的优选方法是在平坦化之前在垂直方向上浅沉积到沉积的SiO 2层中。 该工艺与沟槽隔离区自对准。

    Packing density for flash memories
    19.
    发明授权
    Packing density for flash memories 失效
    闪存的包装密度

    公开(公告)号：US5622881A

    公开(公告)日：1997-04-22

    申请号：US319393

    申请日：1994-10-06

    申请人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    发明人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

    摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

    摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

    Isolation structure using liquid phase oxide deposition
    20.
    发明授权
    Isolation structure using liquid phase oxide deposition 失效
    使用液相氧化物沉积的隔离结构

    公开(公告)号：US5516721A

    公开(公告)日：1996-05-14

    申请号：US393599

    申请日：1995-02-23

    申请人： Carol Galli ,  Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard

    发明人： Carol Galli ,  Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard

    IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L27/08 ,  H01L29/00

    CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/02282

    摘要： A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.

    摘要翻译： 浅沟槽隔离结构通过具有减少步数和热量预算的工艺形成，通过用绝缘半导体氧化物的液相沉积填充沟槽并热处理沉积物以在层间的界面处形成高质量的热氧化物层 沉积的氧化物和沟槽延伸到其中的半导体材料（例如衬底）的主体。 该方法产生具有减小的应力和降低电荷泄漏倾向的隔离结构。 该结构可以容易且容易地平坦化，特别是如果抛光停止层施加在半导体材料的主体上并且空隙和沉积的氧化物的污染基本上通过在孔的体积上的沟槽上的自对准沉积而被消除 抗蚀剂用于形成沟槽。