公开(公告)号：US20190341352A1

公开(公告)日：2019-11-07

申请号：US15968774

申请日：2018-05-02

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Chin-Kwan KIM ,  Jaehyun YEON ,  Manuel ALDRETE ,  David Fraser RAE

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683 ,  H01L21/3105 ,  H01L23/29

Abstract: A semiconductor package comprises a substrate, a die mounted on the substrate, and a mold formed over the die and on the substrate, the mold having a top surface and a plurality of tapered side surfaces, wherein the tapered side surfaces provide uniform thickness of an electromagnetic interference (EMI) shielding film.

公开(公告)号：US20160093567A1

公开(公告)日：2016-03-31

申请号：US14498397

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  Rajneesh KUMAR ,  Layal ROUHANA ,  Joan Rey V. BUOT ,  Omar James BCHIR

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76834 ,  H01L21/76898 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5389 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15333 ,  H01L2924/19041 ,  H01L2924/19106

Abstract: A semiconductor substrate according to some examples of the disclosure may include a substrate with a cavity in a top surface of the substrate, a plurality of cavity interconnections embedded below a bottom surface of the cavity and extending to a bottom surface of the substrate, and a plurality of side interconnections to either side of the cavity extending from the top surface of the substrate to the bottom surface of the substrate. Each of the plurality of side interconnections may include an electrically conductive stop etch layer in the same horizontal plane as the bottom of the cavity.

Abstract translation: 根据本公开的一些示例的半导体衬底可以包括在衬底的顶表面中具有空腔的衬底，多个腔互连嵌入在腔的底表面下方并延伸到衬底的底表面，并且 多个侧面互连到空腔的任一侧，从衬底的顶表面延伸到衬底的底表面。 多个侧面互连中的每一个可以包括在与空腔的底部相同的水平平面中的导电停止蚀刻层。

公开(公告)号：US20220131281A1

公开(公告)日：2022-04-28

申请号：US17568596

申请日：2022-01-04

Applicant: QUALCOMM Incorporated

Inventor： Milind SHAH ,  Chin-Kwan KIM ,  Jaehyun YEON ,  Rajneesh KUMAR ,  Suhyung HWANG

IPC: H01Q23/00 ,  H01Q21/06 ,  H01Q21/30 ,  H01Q1/24 ,  H01Q9/04

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate. The active circuit includes a power management (PM) chip and a radio frequency (RF) chip coupled to a second package substrate coupled to the first package substrate.

公开(公告)号：US20200091062A1

公开(公告)日：2020-03-19

申请号：US16131224

申请日：2018-09-14

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun YEON ,  Hong Bok WE ,  Chin-Kwan KIM ,  Kuiwon KANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/68 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

Abstract: Certain aspects of the present disclosure provide techniques for forming a cavity with various conductive pad interconnections for receiving an electronic component in an integrated circuit. One example method of fabricating an integrated circuit generally includes forming a conductive metal above a first substrate layer, forming a barrier metal above the conductive metal, disposing at least one second substrate layer above the barrier metal, forming a cavity in the at least one second substrate layer by using a laser to expose the barrier metal and the conductive metal in the cavity, and etching the conductive metal in the form of a conductive pad pattern for coupling the conductive metal to an electronic component.

公开(公告)号：US20170084523A1

公开(公告)日：2017-03-23

申请号：US14861619

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Jie FU ,  Daeik Daniel KIM ,  Manuel ALDRETE ,  Chin-Kwan KIM ,  David BERDY ,  Niranjan Sunil MUDAKATTE ,  Changhan YUN ,  Je-Hsiung LAN ,  Jonghae KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/49805 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01R12/79 ,  H01L2224/81

Abstract: Conventional ways of coupling die packages to external devices include providing contacts on a separate area on a printed circuit board (PCB). These PCB contacts are configured to mate with connector contacts of a connector to enable coupling with external devices. Unfortunately, the PCB contacts take up significant amount of area of the PCB. Also, the connection can suffer from parasitic losses and signal integrity can be compromised. An on-package connection is proposed to address the short comings of the conventional ways. The on-package connection enables a die package to connect directly with the connector. This removes the need to provide a separate area for PCB contacts. Also, parasitic losses are minimized and signal integrity is enhanced.

公开(公告)号：US20160247754A1

公开(公告)日：2016-08-25

申请号：US14859318

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jie FU ,  Chin-Kwan KIM ,  Manuel ALDRETE ,  Milind Pravin SHAH ,  Dwayne Richard SHIRLEY

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.

Abstract translation: 集成电路封装包括具有多个导电触点和多个导电柱（例如铜柱）的基板/插入件组件，其电耦合到衬底/插入器组件中的至少一些导电触点。 导电柱被诸如可光成像电介质（PID）的保护电介质包围。 集成电路管芯可以设置在由电介质包围的内部空间内的衬底/插入件组件上。 可以在封装封装（POP）配置中提供附加的集成电路管芯。

公开(公告)号：US20150187731A1

公开(公告)日：2015-07-02

申请号：US14141342

申请日：2013-12-26

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Kyu-Pyung HWANG ,  Chin-Kwan KIM ,  Young Kyu SONG ,  Hong Bok WE

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/4985 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15313

Abstract: A high-speed, high-density Input/Output bridge couples dies on a substrate to each other using a flexible connector that is attached to the substrate using solder balls disposed in openings in the substrate. Thus, the bulky, male-to-female connectors and/or silicon bridges are eliminated while still permitting dies disposed on the substrate to be coupled together.

Abstract translation: 高速，高密度输入/输出桥接器使用使用设置在基板中的开口中的焊球附接到基板的柔性连接器将基板上的管芯相互连接。 因此，消除了庞大的公对母连接器和/或硅桥，同时仍然允许设置在衬底上的管芯耦合在一起。

公开(公告)号：US20230352390A1

公开(公告)日：2023-11-02

申请号：US17735075

申请日：2022-05-02

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  Joan Rey Villarba BUOT ,  Zhijie WANG ,  Marcus HSU ,  Sang-Jae LEE ,  Kuiwon KANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L21/4857 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L24/32 ,  H01L2224/32237 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/83 ,  H01L2224/83192 ,  H01L2224/81815 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L23/49822

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a bump pad interconnect. The bump pad interconnect comprises a profile cross section that has a trapezoid shape. The integrated device is coupled to the substrate through the bump pad interconnect. The bump pad interconnect is located in a cavity of the at least one dielectric layer of the substrate.

公开(公告)号：US20220384328A1

公开(公告)日：2022-12-01

申请号：US17334610

申请日：2021-05-28

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Hong Bok WE ,  Chin-Kwan KIM ,  Milind SHAH

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.

公开(公告)号：US20210376493A1

公开(公告)日：2021-12-02

申请号：US16886086

申请日：2020-05-28

Applicant: QUALCOMM Incorporated

Inventor： Milind SHAH ,  Chin-Kwan KIM ,  Jaehyun YEON ,  Rajneesh KUMAR ,  Suhyung HWANG

IPC: H01Q23/00 ,  H01Q21/30 ,  H01Q21/06

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate.