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    Nonvolatile memory device with on-die control and data signal termination
    13.
    发明授权
    Nonvolatile memory device with on-die control and data signal termination 有权
    具有片上控制和数据信号终止的非易失性存储器件

    公开(公告)号：US09306564B2

    公开(公告)日：2016-04-05

    申请号：US14695260

    申请日：2015-04-24

    Applicant: Rambus Inc.

    Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

    IPC: H03K17/16 ,  H03K19/00 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  G11C11/419 ,  G11C16/26 ,  G11C11/41 ,  G11C11/4063 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G11C16/32

    CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

    Abstract: In a non-volatile memory device having an array of non-volatile storage elements, control information received via one or more control input nodes indicates, at different times, that (i) data signals representative of data to be stored within the array of non-volatile storage elements are to be received via a plurality of input/output (I/O) nodes of the non-volatile memory device, and (ii) data signals representative of data read from the array of non-volatile storage elements are to be output via the plurality of I/O nodes. First termination elements are switchably coupled to and decoupled from the I/O nodes based at least in part on the control information, and second termination elements are switchably coupled to and decoupled from the one or more control input nodes based at least in part on the control information.

    Abstract translation: 在具有非易失性存储元件的阵列的非易失性存储器件中，经由一个或多个控制输入节点接收的控制信息在不同时间指示（i）表示要存储在非阵列阵列内的数据的数据信号， 非挥发性存储元件将通过非易失性存储器件的多个输入/输出（I / O）节点接收，并且（ii）代表从非易失性存储元件阵列读取的数据的数据信号是 通过多个I / O节点输出。 至少部分地基于控制信息，第一终端元件可切换地耦合到I / O节点并从I / O节点去耦，并且第二终端元件至少部分地基于控制信息而切换地耦合到一个或多个控制输入节点并从该一个或多个控制输入节点去耦 控制信息。

    Reducing memory refresh exit time
    15.
    发明授权
    Reducing memory refresh exit time 有权
    减少内存刷新退出时间

    公开(公告)号：US09007862B2

    公开(公告)日：2015-04-14

    申请号：US13938130

    申请日：2013-07-09

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness ,  Ian P. Shaeffer ,  James E. Harris

    IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

    CPC classification number: G11C7/00 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40622

    Abstract: Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

    Abstract translation: 诸如存储器控制器和存储器设备的存储器系统的组件通过控制存储器件的刷新定时来减少退出自刷新模式的延迟。 存储器件包括存储器核。 存储装置的接口电路接收指示间歇刷新事件的外部刷新信号。 存储器件的刷新电路产生指示存储器件的内部刷新事件的内部刷新信号。 存储器件的刷新控制电路响应于内部刷新事件，在相对于由外部刷新信号指示的间歇刷新事件的时间，对存储器核心的一部分执行刷新操作。

    PROCESS FOR MAKING A SEMICONDUCTOR SYSTEM
    16.
    发明申请
    PROCESS FOR MAKING A SEMICONDUCTOR SYSTEM 有权
    制造半导体系统的工艺

    公开(公告)号：US20140329359A1

    公开(公告)日：2014-11-06

    申请号：US14272295

    申请日：2014-05-07

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

    IPC: H01L21/768

    CPC classification number: H01L21/768 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00

    Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.

    Abstract translation: 包括第一设备和第二设备的多个设备具有操作电路和相对的第一和第二表面。 第一和第二电触点形成在第一表面处，而在与第一电触头相对的第二表面处形成第三电接触。 第一电触头电连接到操作电路，并且第二电触头电连接到第三电触头。 随后堆叠第一装置和第二装置，使得第二装置的第一表面位于第一装置的第二表面附近，使得第二装置的第一电触点与第一装置的第三电触点对准 。 第二器件的第一电接触电连接到第一器件的第三电接触件。

    MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
    19.
    发明申请
    MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT 有权

    公开(公告)号：US20220343956A1

    公开(公告)日：2022-10-27

    申请号：US17705039

    申请日：2022-03-25

    Applicant: Rambus Inc.

    Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

    IPC: G11C7/10 ,  G06F13/16 ,  G06F12/00

    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

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