公开(公告)号：US10339999B2

公开(公告)日：2019-07-02

申请号：US16011539

申请日：2018-06-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52 ,  G11C29/04

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20250021497A1

公开(公告)日：2025-01-16

申请号：US18794704

申请日：2024-08-05

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright

IPC: G06F13/16 ,  G06F11/07 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F13/40

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

公开(公告)号：US12066957B2

公开(公告)日：2024-08-20

申请号：US18130355

申请日：2023-04-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1684 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/0784 ,  G06F11/079 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1658 ,  G06F11/2007 ,  G06F13/4027 ,  Y02D10/00

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

公开(公告)号：US11967364B2

公开(公告)日：2024-04-23

申请号：US18203511

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G06F11/10 ,  G11C7/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20220148643A1

公开(公告)日：2022-05-12

申请号：US17532745

申请日：2021-11-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas A. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/00 ,  H01L25/065 ,  H01L25/10 ,  G11C11/4096 ,  H01L25/18

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US20190294502A1

公开(公告)日：2019-09-26

申请号：US16290759

申请日：2019-03-01

Applicant: Rambus Inc.

Inventor： Kenneth L. Wright ,  Frederick A. Ware

IPC: G06F11/14 ,  G06F13/40 ,  G06F11/00 ,  H01L25/065 ,  H01L25/10 ,  G06F3/06 ,  H01L23/00 ,  G06F13/16

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

公开(公告)号：US20180267911A1

公开(公告)日：2018-09-20

申请号：US15761746

申请日：2016-09-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright ,  John Eric Linstadt ,  Craig Hampel

IPC: G06F13/16 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G06F12/0895 ,  G06F13/28

CPC classification number: G06F13/1678 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1068 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0895 ,  G06F13/28 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/403 ,  G11C7/10 ,  G11C29/52

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

公开(公告)号：US09997233B1

公开(公告)日：2018-06-12

申请号：US15285974

申请日：2016-10-05

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/10 ,  G06F12/14 ,  G06F13/16

CPC classification number: G11C11/4093 ,  G06F12/1433 ,  G06F13/1673 ,  G06F13/1678 ,  G06F2212/1052 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/22 ,  G11C29/32 ,  G11C29/38

Abstract: In a memory module having a buffer component, a plurality of data signaling paths and a plurality of memory dies each coupled to a respective one of the data signaling paths, the buffer component receives and stores a first configuration value that specifies a memory-die quantity N, where N is permitted to range from a first value corresponding to the quantity of the data signaling paths to at least one value less than the first value. The buffer component further receives a memory read command and enables, in accordance with the first configuration value, a quantity N of the memory dies to output read data in response to the memory read command.

公开(公告)号：US20170091040A1

公开(公告)日：2017-03-30

申请号：US15260880

申请日：2016-09-09

Applicant: Rambus Inc.

Inventor： Kenneth L. Wright ,  Frederick A. Ware

IPC: G06F11/14 ,  G06F13/40 ,  G06F13/16 ,  H01L23/00 ,  G06F3/06

CPC classification number: G06F11/142 ,  G06F3/0617 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/00 ,  G06F13/1673 ,  G06F13/4068 ,  G06F2201/805 ,  G06F2201/82 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

公开(公告)号：US20230359526A1

公开(公告)日：2023-11-09

申请号：US18203576

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Kenneth L. Wright ,  Frederick A. Ware

IPC: G06F11/14 ,  H01L23/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G06F11/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: G06F11/142 ,  H01L24/17 ,  H01L24/48 ,  G06F3/0617 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1673 ,  G06F13/4068 ,  G06F3/0634 ,  G06F11/00 ,  H01L24/00 ,  H01L25/0657 ,  H01L25/105 ,  H01L2924/1436 ,  G06F2201/805 ,  G06F2201/82 ,  H01L2924/00014 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/15311 ,  G06F11/1423

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.