公开(公告)号：US20190131226A1

公开(公告)日：2019-05-02

申请号：US15978727

申请日：2018-05-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jeong Ho LEE ,  Myung Sam KANG ,  Young Gwan KO ,  Jin Su KIM ,  Shang Hoon SEO ,  Jeong Il LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49822 ,  H01L23/3157 ,  H01L23/49811 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/18 ,  H01L2224/221 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K1/185 ,  H01L2924/0001

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion, and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other. The active surface of the semiconductor chip and an upper surface of the encapsulant have a step portion therebetween.

公开(公告)号：US20190122991A1

公开(公告)日：2019-04-25

申请号：US15972820

申请日：2018-05-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Ki Ju LEE ,  Jin Su KIM

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes: a connection member having first and second surfaces opposing each other and including a redistribution layer; a support member disposed on the first surface of the connection member, including a cavity, and having an inner sidewall surrounding the cavity of which an upper region is chamfered; a semiconductor chip disposed on the connection member in the cavity and having connection pads electrically connected to the redistribution layer; at least one electronic component disposed between the semiconductor chip and the inner sidewall and having connection terminals electrically connected to the redistribution layer; and an encapsulant encapsulating the semiconductor chip and the at least one electronic component disposed in the cavity.

公开(公告)号：US20170033039A1

公开(公告)日：2017-02-02

申请号：US15074376

申请日：2016-03-18

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Ki Ju LEE ,  Jun Woo MYUNG ,  No Il PARK ,  Jin Su KIM ,  Eung Suek LEE ,  Jae Hyun LIM

IPC: H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1531 ,  H01L2924/1532 ,  H01L2924/1533 ,  H01L2924/19106

Abstract: A semiconductor package includes a first substrate, a pattern layer disposed on the first substrate, a first chip member disposed on a surface of the first substrate, lead frames mounted on the first substrate surrounding the first chip member, and a first encapsulation layer disposed on the first substrate, encapsulating the first chip member and the lead frame, wherein upper end portions of the lead frame and the first encapsulation layer are removed, and lead frame columns are exposed through the first encapsulation layer.

Abstract translation: 半导体封装包括第一衬底，设置在第一衬底上的图案层，设置在第一衬底的表面上的第一芯片构件，安装在围绕第一芯片构件的第一衬底上的引线框架和设置在第一衬底上的第一封装层 封装第一芯片构件和引线框架的第一衬底，其中引线框架和第一封装层的上端部分被去除，并且引线框架柱通过第一封装层露出。

公开(公告)号：US20160353572A1

公开(公告)日：2016-12-01

申请号：US15016136

申请日：2016-02-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hyun LIM ,  Jong Man KIM ,  Jin Su KIM ,  Heung Woo PARK ,  Sun Ho KIM ,  Jung Gon CHOI

IPC: H05K1/11 ,  H05K3/46 ,  H05K1/02

Abstract: A printed circuit board, a semiconductor package, and a method of producing the same are provided. The printed circuit board (PCB) includes an insulating layer and a circuit layer including metal pads exposed on a side surface and a lower surface of the insulating layer.

Abstract translation: 提供一种印刷电路板，半导体封装及其制造方法。 印刷电路板（PCB）包括绝缘层和包括暴露在绝缘层的侧表面和下表面上的金属焊盘的电路层。

公开(公告)号：US20190164895A1

公开(公告)日：2019-05-30

申请号：US15986302

申请日：2018-05-22

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jin Su KIM ,  Jeong Ho LEE ,  Shang Hoon SEO ,  Bong Ju CHO

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3025 ,  H01L2924/3511

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a guide pattern disposed adjacent to a wall of the recess portion and disposed in the frame. An edge of the bottom surface of the recess portion has a groove portion.

公开(公告)号：US20190131285A1

公开(公告)日：2019-05-02

申请号：US15900568

申请日：2018-02-20

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yeong A KIM ,  Eun Sil KIM ,  Young Gwan KO ,  Akihisa KUROYANAGI ,  Jin Su KIM ,  Jun Woo MYUNG

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L49/02 ,  H01L21/56 ,  H01L21/48 ,  H01L21/52

Abstract: A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.

公开(公告)号：US20190013276A1

公开(公告)日：2019-01-10

申请号：US15802131

申请日：2017-11-02

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Han Ul LEE ,  Jin Su KIM ,  Young Gwan KO

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68345 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A semiconductor device includes a semiconductor chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the semiconductor chip, a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads, a passivation layer disposed on the connection member, and an under bump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad embedded in the passivation layer and having a recess portion, and a UBM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.

公开(公告)号：US20170005032A1

公开(公告)日：2017-01-05

申请号：US14991589

申请日：2016-01-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jin Su KIM ,  Tae Gu KIM ,  Sung Ho KIM

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/33 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/81

Abstract: A lead frame and a stack package module including the same are provided. The lead frame including a lower-end coupling portion coupled to a lower package through soldering, and an upper-end connecting portion contacting a side surface groove formed in a side surface of an upper package to support the upper package.

Abstract translation: 提供了包括它的引线框架和堆叠封装模块。 引线框架包括通过焊接耦合到下封装的下端耦合部分，以及接触形成在上封装的侧表面中的侧表面槽的上端连接部分，以支撑上封装。

公开(公告)号：US20190172781A1

公开(公告)日：2019-06-06

申请号：US15988893

申请日：2018-05-24

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jeong Il LEE ,  Jeong Ho LEE ,  Jin Su KIM ,  Bong Ju CHO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/495

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers disposed on the insulating layers, and connection via layers penetrating through the insulating layers and electrically connecting the wiring layers to each other, and having a recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and an active surface of the semiconductor chip and including one or more redistribution layers electrically connecting the wiring layers and the connection pads to each other, in which the recess portion includes walls having different inclined angles.

公开(公告)号：US20160315027A1

公开(公告)日：2016-10-27

申请号：US15003473

申请日：2016-01-21

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jong In RYU ,  Ki Joo SIM ,  Do Jae YOO ,  Ki Ju LEE ,  Jin Su KIM

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/768 ,  H01L23/538 ,  H01L21/268

CPC classification number: H01L23/3121 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/16 ,  H01L23/293 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106

Abstract: A semiconductor package and manufacturing method thereof includes a chip member installed on an upper surface, a lower surface, or both of a substrate. The semiconductor package and manufacturing method thereof also include a mold part stacked embedding the chip member, a connection member disposed at a center portion of the mold part, and a solder part formed on a portion of the connection member.

Abstract translation: 半导体封装及其制造方法包括安装在基板的上表面，下表面或两者上的芯片构件。 半导体封装及其制造方法还包括堆叠嵌入芯片部件的模具部件，设置在模具部件的中心部分的连接部件和形成在连接部件的一部分上的焊接部件。