公开(公告)号：US20130277720A1

公开(公告)日：2013-10-24

申请号：US13780855

申请日：2013-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-cheol KIM ,  Cheol KIM ,  Jaehun SEO ,  YooJung LEE ,  Kisoo CHANG ,  Siyoung CHOI

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/7851

Abstract: Field effect transistors include a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode.

Abstract translation: 场效应晶体管包括基板上的源极区域和漏极区域，从基板的顶面突出的翅片基底，从翅片基底向上延伸并将源极区域与漏极区域连接的多个翅片部分， 翅片部分之间的电极以及翅片部分和栅电极之间的栅极电介质。

公开(公告)号：US20220302109A1

公开(公告)日：2022-09-22

申请号：US17502554

申请日：2021-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol KIM

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device including a substrate, first and second active patterns, each including first and second side walls, a field insulation layer surrounding side walls of each of the first and second active patterns, a first dam between the first and second active patterns and having a lower surface lower than an upper surface of the field insulation layer, a second dam spaced apart from the first side wall of the first active pattern and having a lower surface lower than the upper surface of the field insulation layer, a first gate electrode on the first dam between the first and second active patterns, a second gate electrode spaced apart from the first gate electrode, and a first gate cut spaced apart from each of the first side walls of each of the first and second active patterns and intersecting each of the first and second gate electrodes.

公开(公告)号：US20220254650A1

公开(公告)日：2022-08-11

申请号：US17517304

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Young CHOI ,  Sung Min KIM ,  Cheol KIM ,  Hyo Jin KIM ,  Dae Won HA ,  Dong Woo HAN

IPC: H01L21/3213 ,  H01L21/308

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

公开(公告)号：US20220077285A1

公开(公告)日：2022-03-10

申请号：US17528251

申请日：2021-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hyun PARK ,  Kye-hyun BAEK ,  Yong-ho JEON ,  Cheol KIM ,  Sung-il PARK ,  Yun-il LEE ,  Hyung-suk LEE

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

公开(公告)号：US20170040221A1

公开(公告)日：2017-02-09

申请号：US15196870

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol KIM ,  Dong-Hoon KHANG ,  Do-Hyoung KIM ,  Seung-Jin MUN ,  Yong-Joon CHOI ,  Seung-Mo HA

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3115

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/0273 ,  H01L21/0275 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31155 ,  H01L29/66795

Abstract: Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.

Abstract translation: 制造半导体器件的方法包括在复合膜上形成复合膜，形成粗糙图案，通过使粗糙图案经受离子注入和等离子体处理形成平滑图案，并使用平滑图案将复合膜图案化为第一 面具。

公开(公告)号：US20160247925A1

公开(公告)日：2016-08-25

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/306 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US20160148656A1

公开(公告)日：2016-05-26

申请号：US14803119

申请日：2015-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol KIM ,  Young-soo SOHN ,  Sang-Ho SHIN

IPC: G11C7/10 ,  H01L23/525 ,  G11C8/06 ,  G11C5/06 ,  G11C7/06 ,  H01L25/065 ,  G11C5/02

CPC classification number: G11C8/06 ,  G11C29/76 ,  G11C29/785 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit.

Abstract translation: 存储器芯片包括芯片输入 - 输出焊盘单元，多个半导体管芯。 芯片输入输出焊盘单元包括连接到外部设备的多个输入输出引脚，并且多个半导体管芯分别连接到芯片输入 - 输出焊盘单元并具有完全存储器容量。 每个半导体管芯包括管芯输入 - 输出焊盘单元，存储区域和转换块。 管芯输入 - 输出焊盘单元包括分别连接到芯片输入 - 输出焊盘单元的输入 - 输出引脚的多个输入 - 输出端子。 存储器区域包括对应于全部存储器容量的一部分的激活区域和对应于完整存储器容量的剩余部分的去激活区域。 转换块将去激活区域之外的激活区域连接到管芯输入 - 输出焊盘单元。

公开(公告)号：US20160064380A1

公开(公告)日：2016-03-03

申请号：US14934119

申请日：2015-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.