公开(公告)号：US20200335487A1

公开(公告)日：2020-10-22

申请号：US16917526

申请日：2020-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Fei ZHOU

IPC: H01L25/18 ,  H01L29/04 ,  H01L29/16 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.

公开(公告)号：US20200286907A1

公开(公告)日：2020-09-10

申请号：US16882957

申请日：2020-05-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun GE ,  Yanli ZHANG ,  Fei ZHOU ,  Raghuveer S. MAKALA

IPC: H01L27/11568 ,  H01L29/51 ,  H01L29/792 ,  H01L27/1159 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

公开(公告)号：US20200152655A1

公开(公告)日：2020-05-14

申请号：US16183920

申请日：2018-11-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/768

Abstract: A vertical repetition of a unit layer stack including an insulating layer, a sacrificial material layer, and a nucleation promoter layer is formed over a substrate. Memory stack structures are formed through the vertical repetition. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the nucleation promoter layers within the vertical repetition. Electrically conductive layers are formed in the backside recesses by selectively growing a metallic material from physically exposed surfaces of the nucleation promoter layers while suppressing growth of the metallic material from physically exposed surfaces of the insulating layers.

公开(公告)号：US20170278859A1

公开(公告)日：2017-09-28

申请号：US15250185

申请日：2016-08-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Somesh PERI ,  Masanori TSUTSUMI ,  Keerti SHUKLA ,  Yusuke IKAWA ,  Kiyohiko SAKAKIBARA ,  Eisuke TAKII

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02326 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

公开(公告)号：US20240332177A1

公开(公告)日：2024-10-03

申请号：US18362706

申请日：2023-07-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo NAKAMURA ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, where a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle, and memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.

公开(公告)号：US20240237346A1

公开(公告)日：2024-07-11

申请号：US18355888

申请日：2023-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Fei ZHOU ,  Bing ZHOU ,  Senaka KANAKAMEDALA ,  Roshan Jayakhar TIRUKKONDA ,  Kartik SONDHI

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers including a first insulating material and sacrificial material layers including a first sacrificial material over a substrate, forming a memory opening through the alternating stack, performing a first selective material deposition process that selectively grows a second sacrificial material from physically exposed surfaces of the sacrificial material layers to form a vertical stack of sacrificial material portions; forming a memory opening fill structure in the memory opening, where the memory opening fill structure includes a vertical stack of memory elements and a vertical semiconductor channel, and replacing a combination of the vertical stack of sacrificial material portions and the sacrificial material layers with electrically conductive layers.

公开(公告)号：US20240179897A1

公开(公告)日：2024-05-30

申请号：US18351205

申请日：2023-07-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Fei ZHOU

IPC: H10B41/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer, a continuous charge storage material layer vertically extending through a plurality of the electrically conductive layers, a vertical stack of discrete charge storage elements located at levels of the electrically conductive layers and contacting a respective surface segment of an outer sidewall of the continuous charge storage material layer, and a vertical stack of discrete blocking dielectric material portions containing silicon atoms and oxygen atoms and located at the levels of the electrically conductive layers and vertically spaced apart from each other.

公开(公告)号：US20230301077A1

公开(公告)日：2023-09-21

申请号：US17655272

申请日：2022-03-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Masanori TSUTSUMI ,  Fei ZHOU

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/04

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/0483

Abstract: A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material layer and the vertical semiconductor channel.

公开(公告)号：US20230223267A1

公开(公告)日：2023-07-13

申请号：US17573466

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Yujin TERASAWA ,  Naoki TAKEGUCHI ,  Kensuke YAMAGUCHI

IPC: H01L21/285 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/24 ,  H01L21/768 ,  C23C16/14 ,  C23C16/455

CPC classification number: H01L21/28568 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/2481 ,  H01L21/76876 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/76846

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

公开(公告)号：US20230128682A1

公开(公告)日：2023-04-27

申请号：US18145275

申请日：2022-12-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Fei ZHOU

IPC: H10B41/27 ,  G11C16/04 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a memory material layer having a straight inner cylindrical sidewall that vertically extends through a plurality of electrically conductive layers within the alternating stack without lateral undulation and a laterally-undulating outer sidewall having outward lateral protrusions at levels of the plurality of electrically conductive layers.