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    WINDOW PROGRAM VERIFY TO REDUCE DATA LATCH USAGE IN MEMORY DEVICE
    11.
    发明申请
    WINDOW PROGRAM VERIFY TO REDUCE DATA LATCH USAGE IN MEMORY DEVICE 有权

    公开(公告)号：US20220415415A1

    公开(公告)日：2022-12-29

    申请号：US17355615

    申请日：2021-06-23

    Applicant: SanDisk Technologies LLC

    Inventor： Tai-Yuan Tseng ,  Chia-Kai Chou ,  Iris Lu

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C7/06

    Abstract: Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.

    State adaptive predictive programming
    13.
    发明授权
    State adaptive predictive programming 有权

    公开(公告)号：US10748622B2

    公开(公告)日：2020-08-18

    申请号：US16283464

    申请日：2019-02-22

    Applicant: SanDisk Technologies LLC

    Inventor： Lei Lin ,  Zhuojie Li ,  Tai-Yuan Tseng ,  Henry Chin ,  Gerrit Jan Hemink

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.

    Sense circuit with two-step clock signal for consecutive sensing
    15.
    发明授权
    Sense circuit with two-step clock signal for consecutive sensing 有权

    公开(公告)号：US10366729B2

    公开(公告)日：2019-07-30

    申请号：US15630079

    申请日：2017-06-22

    Applicant: SanDisk Technologies LLC

    Inventor： Tai-Yuan Tseng ,  Anirudh Amarnath

    IPC: G11C11/16 ,  G11C7/08 ,  G11C7/12 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C13/00 ,  G11C11/56 ,  G11C16/08 ,  G11C16/32

    Abstract: A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be lower and higher verify voltages of a data state in a programming operation, or two read levels of a read operation. A sense node is charged up to a peak level by a pre-charge voltage and by capacitive coupling. The sense node then discharges into the bit line. The sense node voltage is decreased first and second times by capacitive coupling after which first and second bits of data are output based on a level of the sense node. The first and second bits indicate a level of the sense node relative to the lower and higher verify voltages, respectively.

    Sense circuit with two sense nodes for cascade sensing
    16.
    发明授权
    Sense circuit with two sense nodes for cascade sensing 有权

    公开(公告)号：US10121522B1

    公开(公告)日：2018-11-06

    申请号：US15630089

    申请日：2017-06-22

    Applicant: SanDisk Technologies LLC

    Inventor： Tai-Yuan Tseng ,  Anirudh Amarnath ,  Yan Li

    IPC: G11C16/10 ,  G11C7/08 ,  G11C11/16 ,  G11C13/00

    Abstract: A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be higher and lower verify voltages of a data state in a programming operation, or two read levels of a read operation. Two sense nodes which are connected in a cascade configuration such that a first sense node discharges into the bit line initially, and a second sense node may or may not discharge into the bit line, depending on the level to which the first node has discharged. First and second bits of data can be output from the sense circuit based on the levels of the first and second sense nodes to indicate the threshold voltage of the memory cell relative to the higher and lower verify voltages, respectively.

    NON-VOLATILE MEMORY WITH ISOLATION LATCH SHARED BETWEEN DATA LATCH GROUPS
    18.
    发明公开
    NON-VOLATILE MEMORY WITH ISOLATION LATCH SHARED BETWEEN DATA LATCH GROUPS 审中-公开

    公开(公告)号：US20230368852A1

    公开(公告)日：2023-11-16

    申请号：US17745120

    申请日：2022-05-16

    Applicant: SanDisk Technologies LLC

    Inventor： Kei Kitamura ,  Iris Lu ,  Tai-Yuan Tseng

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C7/10

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/24 ,  G11C7/1048 ,  G11C7/1039

    Abstract: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.

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