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公开(公告)号：US20230282288A1
公开(公告)日：2023-09-07
申请号：US17685613
申请日：2022-03-03
发明人： Xiang Yang , Deepanshu Dutta , Ohwon Kwon , James Kai , Yuki Mizutani
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/24
摘要： The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line. During some read operations, this allows the memory device to operate with lower power requirements.
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公开(公告)号：US10256248B2
公开(公告)日：2019-04-09
申请号：US15175450
申请日：2016-06-07
发明人： Zhenyu Lu , Jixin Yu , Johann Alsmeier , Fumiaki Toyama , Yuki Mizutani , Hiroyuki Ogawa , Chun Ge , Daxin Mao , Yanli Zhang , Alexander Chu , Yan Li
IPC分类号： H01L27/11582 , H01L21/48 , H01L23/498 , H01L29/66 , H01L29/792 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region. At least one through-memory-level via structure can be formed through the remaining portions of the spacer dielectric layers and the insulating layers to provide a vertically conductive path through a memory-level assembly.
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公开(公告)号：US20170179026A1
公开(公告)日：2017-06-22
申请号：US15269017
申请日：2016-09-19
发明人： Fumiaki Toyama , Hiroyuki Ogawa , Yoko Furihata , James Kai , Yuki Mizutani , Jixin Yu , Jin Liu , Johann Alsmeier
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768 , H01L27/115
CPC分类号： H01L27/11582 , H01L21/76802 , H01L21/76816 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L27/0288 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.
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公开(公告)号：US11011209B2
公开(公告)日：2021-05-18
申请号：US16589404
申请日：2019-10-01
发明人： Jee-Yeon Kim , Kwang-Ho Kim , Yuki Mizutani , Fumiaki Toyama
IPC分类号： H01L29/76 , G11C5/06 , H01L23/522 , H01L23/528 , H01L23/00 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11519
摘要： A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures. Each metal pad is electrically connected to a respective bit line through a series connection of a respective pad-connection via structure, a respective contact-level metal interconnect, and a respective bit-line-connection via structure.
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公开(公告)号：US09935050B2
公开(公告)日：2018-04-03
申请号：US15634423
申请日：2017-06-27
发明人： Mohan Dunga , Yuki Mizutani , Zhenyu Lu
IPC分类号： H01L29/06 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/24 , H01L23/522 , H01L21/768
CPC分类号： H01L23/528 , H01L21/768 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66666 , H01L29/7883 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A multi-tier memory device includes a first tier structure overlying a substrate and containing a first alternating stack of first insulating layers and first electrically conductive layers, and first memory stack structures each including a first memory film and a first vertical semiconductor channel, a source line overlying the first tier structure, and a second tier structure overlying the source line and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory stack structures each including a second memory film and a second vertical semiconductor channel.
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公开(公告)号：US09929174B1
公开(公告)日：2018-03-27
申请号：US15337235
申请日：2016-10-28
发明人： Yuki Mizutani , Hiroyuki Ogawa , Fumiaki Toyama , Masaaki Higashitani , Fumitaka Amano , Kota Funayama , Akihiro Ueda
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/1157 , H01L29/786 , H01L29/792 , H01L27/11568 , H01L29/06
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L29/0692 , H01L29/78642 , H01L29/7926
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures including a memory film and a vertical semiconductor channel are formed through the alternating stack in an array configuration. Backside trenches extending along a lengthwise direction are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers. Filling of the backside recesses with electrically conductive layers can be performed without voids or with minimal voids by arranging the memory stack structures with a non-uniform pitch. The non-uniform pitch may be along the direction perpendicular to the lengthwise direction such that the nearest neighbor distance among the memory stack structures is at a minimum between the backside trenches. Alternatively or additionally, the pitch may be modulated along the lengthwise direction to provide wider spacing regions that extend perpendicular to the lengthwise direction.
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公开(公告)号：US09922987B1
公开(公告)日：2018-03-20
申请号：US15468732
申请日：2017-03-24
发明人： Yuki Mizutani , James Kai , Fumiaki Toyama , Shigehiro Fujino , Johann Alsmeier
IPC分类号： H01L27/115 , H01L27/11548 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L23/485
CPC分类号： H01L27/11548 , H01L23/485 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： Memory stack structures can be formed through an alternating stack of insulating layers and spacer material layers that are formed as, or are subsequently replaced with, electrically conductive layers. The memory stack structures can be formed as rows having a first pitch. Additional insulating layers and at least one drain select level dielectric layer are formed over the alternating stack. Drain select level openings are formed in rows having a smaller second pitch. Partial replacement of the at least one drain select level dielectric layer forms spaced apart electrically conductive line structures that surround a respective plurality of drain select level openings. Drain select level channel portions are subsequently formed in respective drain select level openings.
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18.发明授权公开(公告)号：US09595338B2
公开(公告)日：2017-03-14
申请号：US14495283
申请日：2014-09-24
发明人： Juan Carlos Lee , Hao Nguyen , Man Mui , Tien-chien Kuo , Yuki Mizutani
摘要： In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.
摘要翻译： 在NAND闪存中，位线预充/放电时间可以是确定程序，擦除和读取性能的主要组成部分。 在常规布置中，位线电平由感测放大器设置，位线通过读出放大器路径被放电到源极线电平。 在这种布置下，基于位线的RC常数，预充电/放电时间由远端（相对于感测放大器）支配。 因此，减少位线预充电/放电时间，从而提高了NAND闪存的性能，从而提高了整体系统的性能。 为了解决这个问题，通过使用虚拟NAND串将额外的路径引入到公共源级别的位线之间。 在基于示例性的基于3D-NAND（BiCS）的实施例中，虚拟NAND串从虚拟块中获取，其中虚拟块可以被放置在整个阵列中以均匀分布放电电流。
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公开(公告)号：US12032837B2
公开(公告)日：2024-07-09
申请号：US17957424
申请日：2022-09-30
IPC分类号： G06F3/06
CPC分类号： G06F3/0626 , G06F3/0629 , G06F3/0679
摘要： A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.
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20.发明授权公开(公告)号：US12004348B2
公开(公告)日：2024-06-04
申请号：US17347810
申请日：2021-06-15
IPC分类号： H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/41 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40
CPC分类号： H10B43/27 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/41 , H10B43/10 , H10B43/35 , H10B43/40
摘要： A bonded assembly includes a memory die that is bonded to a logic die. The memory die includes a three-dimensional memory array located on a memory-side substrate, memory-side dielectric material layers located on the three-dimensional memory array and embedding memory-side metal interconnect structures and memory-side bonding pads, a backside peripheral circuit located on a backside surface of the memory-side substrate, and backside dielectric material layers located on a backside of the memory-side substrate and embedding backside metal interconnect structures. The logic die includes a logic-side peripheral circuit located on a logic-side substrate, and logic-side dielectric material layers located between the logic-side substrate and the memory die and embedding logic-side metal interconnect structures and logic-side bonding pads that are bonded to a respective one of the memory-side bonding pads.
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