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    CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    11.
    发明申请
    CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权
    时钟发生电路和半导体器件包括它们

    公开(公告)号：US20140002149A1

    公开(公告)日：2014-01-02

    申请号：US13711692

    申请日：2012-12-12

    Applicant: SK HYNIX INC.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

    IPC: H03H11/26 ,  H03L7/06

    CPC classification number: H03H11/265 ,  H03L7/06 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/085

    Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.

    Abstract translation: 时钟生成电路包括延迟线，延迟建模块，相位检测块，多更新信号生成块和延迟线。 延迟线延迟输入时钟并产生延迟时钟。 延迟建模块通过建模延迟值将延迟时钟延迟并产生反馈时钟。 相位检测块比较输入时钟和反馈时钟的相位，并产生相位信息，并量化输入时钟和反馈时钟之间的相位差，并产生相位代码。 多更新信号生成块响应于相位代码生成多更新信号。 响应于多更新信号和相位信息，延迟线控制块改变延迟线的延迟量。

    ALL DIGITAL PHASE LOCKED LOOP
    13.
    发明申请
    ALL DIGITAL PHASE LOCKED LOOP 审中-公开

    公开(公告)号：US20180183447A1

    公开(公告)日：2018-06-28

    申请号：US15795703

    申请日：2017-10-27

    Applicant: SK hynix Inc. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

    Inventor： Jae Yoon SIM ,  Min Seob LEE ,  In Hwa JUNG ,  Yong Ju KIM

    IPC: H03L7/099 ,  H03L7/07

    CPC classification number: H03L7/0992 ,  H03L7/07

    Abstract: An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

    SEMICONDUCTOR SYSTEMS
    14.
    发明申请
    SEMICONDUCTOR SYSTEMS 审中-公开

    公开(公告)号：US20180060166A1

    公开(公告)日：2018-03-01

    申请号：US15611151

    申请日：2017-06-01

    Applicant: SK hynix Inc.

    Inventor： Sungeun LEE ,  Jung Hyun KWON ,  Yong Ju KIM ,  Jae Sun LEE ,  JINGZHE XU

    IPC: G06F11/10 ,  H03M13/19 ,  H03M13/15 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/152 ,  H03M13/19

    Abstract: A semiconductor system includes a host and a media controller. The host may generate first host parities from first host data based on an error check matrix. The media controller may include a first input/output (I/O) circuit and a second I/O circuit. The media controller may generate first media data and first media parities based on the first host data and the first host parities. The first I/O circuit may generate, based on the error check matrix, first internal data by correcting errors in the first host data using the first host parities. The second I/O circuit may generate the first media data and the first media parities from the first internal data.

    MEMORY APPARATUS AND METHOD OF WEAR-LEVELING OF A MEMORY APPARATUS
    20.
    发明申请
    MEMORY APPARATUS AND METHOD OF WEAR-LEVELING OF A MEMORY APPARATUS 审中-公开

    公开(公告)号：US20190171561A1

    公开(公告)日：2019-06-06

    申请号：US16271431

    申请日：2019-02-08

    Applicant: SK hynix Inc.

    Inventor： Donggun KIM ,  Yong Ju KIM ,  Do Sun HONG

    IPC: G06F12/02

    Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.

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