公开(公告)号：US10770576B2

公开(公告)日：2020-09-08

申请号：US16154411

申请日：2018-10-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fabio Russo ,  Cristiano Gianluca Stella

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L23/538 ,  H01L23/00 ,  H01L23/495 ,  H01L29/423 ,  H01L29/66 ,  H01L23/485 ,  H01L23/48

Abstract: A MOSFET device is integrated in a body of semiconductor material of a first conductivity type accommodating a body region, of a second conductivity type, and a source region, of the first conductivity type. A gate region extends over the top surface of the body; a source pad extends over the first top surface and is electrically coupled to the source region, a first gate pad extends over the first main surface, alongside the source pad, and is electrically coupled to the gate region; a drain pad extends over the rear surface and is electrically coupled to the body; a second gate pad extends over the rear surface, alongside the drain pad; and a conductive via extends through the body and electrically couples the gate region to the second gate pad.

公开(公告)号：US10720373B2

公开(公告)日：2020-07-21

申请号：US16370193

申请日：2019-03-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Francesco Salamone ,  Cristiano Gianluca Stella

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/433 ,  H01L23/495 ,  H01L23/373 ,  H01L23/48 ,  H01L23/34 ,  H01L23/36 ,  H01L23/42 ,  H01L23/28

Abstract: A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions.

公开(公告)号：US09013878B2

公开(公告)日：2015-04-21

申请号：US13626322

申请日：2012-09-25

Applicant: STMicroelectronics S.r.l.

Inventor： Matteo Sebastiano Dimauro ,  Sebastiano Russo ,  Rosalba Cacciola ,  Cristiano Gianluca Stella

IPC: H05K7/20 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K1/111 ,  H05K3/3431 ,  H05K2201/0373 ,  H05K2201/09663 ,  H05K2201/10166 ,  H05K2201/10969 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49149

Abstract: An electronic system includes an insulating structural element with a coupling surface configured for coupling the electronic system with at least one further electronic system. The electronic system further includes at least one conducting contact element at least partially exposed on the coupling surface. Each conducting contact element has a soldering surface supporting reflow soldering of the conducting contact element with a corresponding further contact element of the further electronic system. In addition, each conducting contact element has at least one lateral surface protruding from the insulating structural element. The soldering surface of the conducting contact element includes at least one channel having an opened end at the protruding lateral surface, the channel configured to facilitate dispersion of waste gas produced during reflow soldering.

Abstract translation: 电子系统包括绝缘结构元件，其具有被配置为将电子系统与至少一个另外的电子系统耦合的耦合表面。 电子系统还包括至少一个至少部分地暴露在耦合表面上的导电接触元件。 每个导电接触元件具有支撑导电接触元件的回流焊接的焊接表面与另外的电子系统的相应的另外的接触元件。 此外，每个导电接触元件具有从绝缘结构元件突出的至少一个侧表面。 导电接触元件的焊接表面包括在突出侧表面具有开口端的至少一个通道，该通道构造成便于在回流焊接期间产生的废气的分散。

公开(公告)号：US20140239413A1

公开(公告)日：2014-08-28

申请号：US14182156

申请日：2014-02-17

Applicant: STMicroelectronics S.r.l.

Inventor： Cristiano Gianluca Stella ,  Fabio Criscione ,  Gaetano Pignataro

IPC: H01L27/02

CPC classification number: H01L27/0251 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/371 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A device includes a first and second transistors integrated in first and second chips. Each chip has opposed rear and front surfaces, and further has a first conduction terminal and a control terminal on the front surface and a second conduction terminal on the rear surface. The first and second transistors are electrically connected in series by having the first conduction terminals of the first and second transistors be electrically connected. The device includes a common package enclosing the first and second chips, the common package having an insulating body with a mounting surface. A heat sink is also enclosed within the insulating body, the heat sink making electrical contact with the first conduction terminals of the first and second chips on the respective front surfaces, so that the first conduction terminals are electrically connected together through the heat sink.

Abstract translation: 一种器件包括集成在第一和第二芯片中的第一和第二晶体管。 每个芯片具有相对的后表面和前表面，并且还具有前表面上的第一导电端子和控制端子以及后表面上的第二导电端子。 第一和第二晶体管通过使第一和第二晶体管的第一导电端子电连接而串联电连接。 该装置包括封装第一和第二芯片的公共封装，公共封装具有带有安装表面的绝缘体。 散热器也封装在绝缘体内，散热片与相应前表面上的第一和第二芯片的第一导电端子电接触，使得第一导电端子通过散热器电连接在一起。

公开(公告)号：US20130083490A1

公开(公告)日：2013-04-04

申请号：US13626229

申请日：2012-09-25

Applicant: STMicroelectronics S.r.l.

Inventor： Cristiano Gianluca Stella ,  Rosalba Cacciola

IPC: H05K1/02 ,  H05K7/20 ,  H05K13/04 ,  H05K7/06

CPC classification number: H05K3/3468 ,  H01L2224/73203 ,  H01L2924/13091 ,  H05K1/111 ,  H05K3/305 ,  H05K2201/09381 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2203/044 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic board includes conducting traces having an upper surface at least partially sunken with respect to a gluing surface of the board. A surface mount technology electronic device for mounting to the board includes insulating windows that define gluing sites within one or more pins. An electronic system is formed by one or more of such surface mount technology electronic devices mounted to electronic board. The devices are attached using a wave soldering technique that flows through channels formed by the sunken conductive traces.

Abstract translation: 电子板包括具有相对于板的胶合表面至少部分凹陷的上表面的导电迹线。 用于安装到板上的表面贴装技术电子器件包括限定一个或多个引脚内的胶合位置的绝缘窗。 电子系统由安装到电子板的一种或多种这样的表面贴装技术电子装置形成。 这些装置使用波峰焊技术连接，该技术流过由凹陷的导电迹线形成的通道。

公开(公告)号：US11830794B2

公开(公告)日：2023-11-28

申请号：US17367086

申请日：2021-07-02

Applicant: STMicroelectronics S.r.l.

Inventor： Cristiano Gianluca Stella ,  Fabio Russo

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49527 ,  H01L23/49562 ,  H01L23/49575

Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

公开(公告)号：US20190326208A1

公开(公告)日：2019-10-24

申请号：US16385928

申请日：2019-04-16

Applicant: STMicroelectronics S.r.l.

Inventor： Cristiano Gianluca Stella ,  Agatino Minotti

IPC: H01L23/498 ,  H01L23/373

Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

公开(公告)号：US20160079092A1

公开(公告)日：2016-03-17

申请号：US14946871

申请日：2015-11-20

Applicant: STMicroelectronics S.r.l.

Inventor： Agatino Minotti ,  Cristiano Gianluca Stella

IPC: H01L21/52 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/52 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49562 ,  H01L2224/32245 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An electronic device includes at least one chip and an insulating body embedding the chip. The electronic device further includes a heat-sink in contact with the chip. The heat-sink includes a plate having a first thickness. A recess is provided in the plate that defines a central portion of the plate having a second thickness less than the first thickness. The chip is mounted to the central region of the heat-sink within the recess. The insulating body includes a surface, such as a mounting surface, including an opening exposing at least a portion of the heat-sink. The device may further include a reophore extending through a side surface of the insulating body, that reophore being in contact with the heat sink.

公开(公告)号：US08890313B2

公开(公告)日：2014-11-18

申请号：US13871857

申请日：2013-04-26

Applicant: STMicroelectronics S.r.l.

Inventor： Cristiano Gianluca Stella ,  Gaetano Pignataro ,  Maurizio Maria Ferrara

IPC: H01L23/24 ,  H01L23/495 ,  H01L23/367 ,  H01L23/433

CPC classification number: H01L23/3677 ,  H01L23/4334 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device includes a first chip and a second chip, where each chip has a first conduction terminal on a first surface and a second conduction terminal on a second surface. An insulating body surrounds the first and second chip, a first heat-sink coupled with the first conduction terminals of the first and second chip, and a second heat-sink coupled with the second conduction terminals of the first and second chip. A portion of the first heat-sink and/or the second heat-sink being exposed from the insulating body. The electronic device includes a first conductive lead and a second conductive lead exposed from the insulating body for through-hole mounting of the electronic device on an electronic board, the first conductive lead being coupled with the first heat-sink and the second conductive lead being coupled with the second heat-sink.

Abstract translation: 电子设备包括第一芯片和第二芯片，其中每个芯片在第一表面上具有第一导电端子，在第二表面上具有第二导电端子。 绝缘体围绕第一和第二芯片，与第一和第二芯片的第一导电端子耦合的第一散热器和与第一和第二芯片的第二导电端子耦合的第二散热器。 第一散热器和/或第二散热器的一部分从绝缘体露出。 电子设备包括从绝缘体暴露的第一导电引线和第二导电引线，用于将电子器件通孔安装在电子板上，第一导电引线与第一散热器耦合，第二导电引线为 加上第二个散热器。

公开(公告)号：US20130285230A1

公开(公告)日：2013-10-31

申请号：US13871861

申请日：2013-04-26

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Cristiano Gianluca Stella ,  Gaetano Pignataro ,  Maurizio Maria Ferrara

IPC: H01L23/34

CPC classification number: H01L23/34 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L25/074 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A power device includes a chip of semiconductor material and a further chip of semiconductor material on each of which at least one power transistor is integrated; each chip comprises a first conduction terminal on a first surface, and a second conduction terminal and a control terminal on a second surface opposite the first surface, and an insulating body embedding said chip and said further chip. In the solution according to one or more embodiments of the present disclosure, the first surface of said chip faces the second surface of said further chip, and the power device further comprises a first heat-sink arranged between said chip and said further chip and electrically coupled with the first conduction terminal of said chip and with the second conduction terminal of said further chip, the control terminal of said further chip being electrically insulated from the first heat-sink.

Abstract translation: 功率器件包括半导体材料芯片和另外的半导体材料芯片，其中至少一个功率晶体管被集成在其中; 每个芯片包括在第一表面上的第一导电端子，以及在与第一表面相对的第二表面上的第二导电端子和控制端子，以及嵌入所述芯片和所述另外的芯片的绝缘体。 在根据本公开的一个或多个实施例的解决方案中，所述芯片的第一表面面向所述另外的芯片的第二表面，并且功率器件还包括布置在所述芯片和所述另外的芯片之间的第一散热器， 与所述芯片的第一导电端子和所述另外芯片的第二导电端子耦合，所述另外芯片的控制端子与第一散热器电绝缘。