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    Row decoder circuit for a phase change non-volatile memory device
    11.
    发明授权
    Row decoder circuit for a phase change non-volatile memory device 有权
    行解码电路用于相变非易失性存储器件

    公开(公告)号：US08982612B2

    公开(公告)日：2015-03-17

    申请号：US13888593

    申请日：2013-05-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Maurizio Francesco Perroni ,  Guido Desandre ,  Salvatore Polizzi ,  Giuseppe Castagna

    IPC: G11C11/00 ,  G11C13/00 ,  G11C8/10

    CPC classification number: G11C13/0028 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/79

    Abstract: A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.

    Abstract translation: 用于相变非易失性存储器件的行解码器电路可以包括以字线布置的存储器单元。 该装置可以被配置为接收高于第一电源电压的第一电源电压和第二电源电压。 行解码器可以包括全局预解码级，其被配置为接收地址信号并且在第二电源电压的范围内产生高电压解码的地址信号，并且基于操作具有基于值的偏置信号。 行解码器可以包括耦合到全局预编码阶段的行解码器级。 行解码器级可以包括：选择驱动单元，被配置为基于高电压解码的地址信号产生块地址信号;以及行驱动单元，被配置为基于块地址生成用于偏置字线的行驱动信号 信号和偏置信号。

    Non volatile memory device with an asymmetric row decoder and method for selecting word lines
    12.
    发明授权
    Non volatile memory device with an asymmetric row decoder and method for selecting word lines 有权

    公开(公告)号：US11380380B2

    公开(公告)日：2022-07-05

    申请号：US17088060

    申请日：2020-11-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fabio Enrico Carlo Disegni ,  Maurizio Francesco Perroni ,  Cesare Torti ,  Guiseppe Scardino

    IPC: G11C8/10 ,  G11C8/08

    Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.

    Non-volatile memory device including a row decoder with a pull-up stage controlled by a current mirror
    13.
    发明授权
    Non-volatile memory device including a row decoder with a pull-up stage controlled by a current mirror 有权

    公开(公告)号：US11289158B2

    公开(公告)日：2022-03-29

    申请号：US17123518

    申请日：2020-12-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fabio Enrico Carlo Disegni ,  Maurizio Francesco Perroni ,  Cesare Torti ,  Davide Manfré

    IPC: G11C13/00

    Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.

    BIT-LINE VOLTAGE GENERATION CIRCUIT FOR A NON-VOLATILE MEMORY DEVICE AND CORRESPONDING METHOD
    14.
    发明申请
    BIT-LINE VOLTAGE GENERATION CIRCUIT FOR A NON-VOLATILE MEMORY DEVICE AND CORRESPONDING METHOD 有权

    公开(公告)号：US20210233582A1

    公开(公告)日：2021-07-29

    申请号：US17159381

    申请日：2021-01-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Michele La Placa ,  Cesare Torti

    IPC: G11C13/00

    Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.

    Address decoder for a non-volatile memory array using MOS selection transistors
    16.
    发明授权
    Address decoder for a non-volatile memory array using MOS selection transistors 有权

    公开(公告)号：US10115462B2

    公开(公告)日：2018-10-30

    申请号：US15474607

    申请日：2017-03-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Salvatore Polizzi ,  Maurizio Francesco Perroni

    IPC: G11C13/00

    Abstract: An address decoder, for a non-volatile memory device provided with a memory array having memory cells arranged in word lines (WL) and bit lines (BL), each memory cell being having a memory element and an access element with a MOS transistor for enabling access to the memory element. Source terminals of the MOS transistors of the access elements of the memory cells of a same word line are connected to a respective source line. The address decoder has a row-decoder circuit and a column-decoder circuit, for selecting and biasing the word lines and the bit lines, respectively, of the memory array with row-driving signals (VWL) and column-driving signals (VBL), respectively. The address decoder has a source-decoder circuit for generating source-driving signals (VSL) for biasing the source lines of the memory array, on the basis of the logic combination of the row-driving signals of associated word lines.

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