公开(公告)号：US10109563B2

公开(公告)日：2018-10-23

申请号：US15399234

申请日：2017-01-05

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Jefferson Talledo ,  Moonlord Manalo ,  Ela Mia Cadag ,  Rammil Seguido

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US09947636B2

公开(公告)日：2018-04-17

申请号：US14293274

申请日：2014-06-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Talledo

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L24/49 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/48096 ,  H01L2224/48097 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8385 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method for making a semiconductor device may include bonding a top lead frame component, having recesses, with a bottom lead frame component to form a lead frame, the top and bottom lead frame components each including metal. The method may include mounting an IC on the lead frame, encapsulating the IC and the lead frame, and removing portions of the bottom lead frame component to define contacts for the IC.

公开(公告)号：US09947612B2

公开(公告)日：2018-04-17

申请号：US14957785

申请日：2015-12-03

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Talledo ,  Rammil Seguido

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49531 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4918 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.

公开(公告)号：US09847281B2

公开(公告)日：2017-12-19

申请号：US14788303

申请日：2015-06-30

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/568 ,  H01L23/293 ,  H01L23/296 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49548 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399

Abstract: Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process.

公开(公告)号：US20170358555A1

公开(公告)日：2017-12-14

申请号：US15181116

申请日：2016-06-13

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Talledo

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81

Abstract: One or more embodiments are directed to stacked packages, such as Package-on-Package (PoP) packages, that are stacked on a flexible folded substrate. The stacked packages have compliant corners. In particular, the stacked packages include an adhesive material at the corners between layers of the folded substrate. The adhesive material has a low modulus of elasticity, such as, for example, a modulus of elasticity of silicone adhesive. The low modulus of elasticity of the adhesive material produces compliant corners of the stacked package. The adhesive material fills openings between the folded substrate that are formed around a bottom semiconductor package of the stack package. In that regard, the bottom semiconductor package may have pulled back or recessed corners and the adhesive material fills the openings formed by the recessed corners. The recessed corners may be any size or shape.

公开(公告)号：US09842828B1

公开(公告)日：2017-12-12

申请号：US15181116

申请日：2016-06-13

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Talledo

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81

Abstract: One or more embodiments are directed to stacked packages, such as Package-on-Package (PoP) packages, that are stacked on a flexible folded substrate. The stacked packages have compliant corners. In particular, the stacked packages include an adhesive material at the corners between layers of the folded substrate. The adhesive material has a low modulus of elasticity, such as, for example, a modulus of elasticity of silicone adhesive. The low modulus of elasticity of the adhesive material produces compliant corners of the stacked package. The adhesive material fills openings between the folded substrate that are formed around a bottom semiconductor package of the stack package. In that regard, the bottom semiconductor package may have pulled back or recessed corners and the adhesive material fills the openings formed by the recessed corners. The recessed corners may be any size or shape.

公开(公告)号：US20170110340A1

公开(公告)日：2017-04-20

申请号：US15392909

申请日：2016-12-28

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo ,  Frederick Ray Gomez

IPC: H01L21/48 ,  H01L21/54 ,  H01L21/78

CPC classification number: H01L21/4842 ,  H01L21/4825 ,  H01L21/54 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/8385 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/10628 ,  H05K2201/10992 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.

公开(公告)号：US20160293523A1

公开(公告)日：2016-10-06

申请号：US14674069

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Talledo ,  Ela Mia Cadag

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49555 ,  H01L23/49562 ,  H01L2224/37599 ,  H01L2224/40 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: An integrated circuit (IC) device may include a leadframe and an IC die having a first surface coupled to the lead frame and a second surface opposite the first surface. The IC device may further include a conductive clip including a first portion coupled to the second surface of the IC die, a second portion coupled to the first portion and extending laterally away from the IC die, and at least one flexible lead coupled to the second portion and looping back under the second portion toward the leadframe. Furthermore, a package may be over the leadframe, IC die, and conductive clip and have an opening therein exposing the at least one flexible lead.

Abstract translation: 集成电路（IC）装置可以包括引线框架和具有耦合到引线框架的第一表面和与第一表面相对的第二表面的IC管芯。 IC器件还可以包括导电夹子，该导电夹子包括耦合到IC芯片的第二表面的第一部分，耦合到第一部分并且横向远离IC芯片延伸的第二部分，以及耦合到第二部分的至少一个柔性引线 并且在第二部分之下环绕回引线框架。 此外，封装可以在引线框架，IC管芯和导电夹子之上，并且在其中具有露出至少一个柔性引线的开口。

公开(公告)号：US11348863B2

公开(公告)日：2022-05-31

申请号：US16706414

申请日：2019-12-06

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: In various embodiments, the present disclosure provides semiconductor packages, devices, and methods. In one embodiment, a device includes a die pad, leads that are spaced apart from the die pad, and a semiconductor die on the die pad. The semiconductor die has a first surface and a second surface opposite the first surface. The second surface faces the die pad. An encapsulant is provided on the semiconductor die, the die pad and the leads, and the encapsulant has a first surface opposite the die pad and the leads, and a second surface opposite the first surface. The second surface of the encapsulant extends between the die pad and an adjacent lead. The second surface of the encapsulant is spaced apart from the first surface of the encapsulant by a first distance, and an exposed surface of the die pad is spaced apart from the first surface of the encapsulant by a second distance that is greater than the first distance.

公开(公告)号：US11270894B2

公开(公告)日：2022-03-08

申请号：US15876046

申请日：2018-01-19

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo ,  Godfrey Dimayuga

IPC: H01L21/48 ,  H05K3/32 ,  H01L23/498 ,  H05K3/28 ,  G01P15/08 ,  H05K3/34 ,  H01L23/31

Abstract: One or more embodiments are directed to methods of forming one or more cantilever pads for semiconductor packages. In one embodiment a recess is formed in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.