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公开(公告)号：US20210320664A1
公开(公告)日：2021-10-14
申请号：US17077891
申请日：2020-10-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Anil Kavala , Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.
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公开(公告)号：US11107512B2
公开(公告)日：2021-08-31
申请号：US17001941
申请日：2020-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byunghoon Jeong , Kyungtae Kang , Jangwoo Lee , Jeongdon Ihm
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号：US12210773B2
公开(公告)日：2025-01-28
申请号：US17528285
申请日：2021-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin Jo , Tongsung Kim , Chiweon Yoon , Seonkyoo Lee , Byunghoon Jeong
Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.
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公开(公告)号：US12073917B2
公开(公告)日：2024-08-27
申请号：US17404510
申请日：2021-08-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tongsung Kim , Youngmin Jo , Manjae Yang , Chiweon Yoon , Junha Lee , Byunghoon Jeong
CPC classification number: G11C7/222 , G06F1/04 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C29/023 , G11C29/028 , G11C5/145
Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.
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公开(公告)号：US11810638B2
公开(公告)日：2023-11-07
申请号：US17410210
申请日：2021-08-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seonkyoo Lee , Chiweon Yoon , Byunghoon Jeong , Youngmin Jo
IPC: G11C7/10 , H01L25/065 , G06F13/42
CPC classification number: G11C7/1048 , H01L25/0657 , G06F13/4282 , G11C2207/12 , H01L2225/06506 , H01L2225/06562
Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.
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Patent Agency Ranking
公开(公告)号：US11756592B2
公开(公告)日：2023-09-12
申请号：US17477931
申请日：2021-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin Jo , Byunghoon Jeong , Tongsung Kim , Chiweon Yoon , Seonkyoo Lee
IPC: G11C7/10
CPC classification number: G11C7/1048 , G11C7/109 , G11C7/1039 , G11C7/1057 , G11C7/1063 , G11C7/1084
Abstract: A memory device includes a memory cell array, a page buffer, a control logic circuit, a plurality of input/output pins, a data bus inversion (DBI) pin, and an interface circuit. The page buffer is connected to the memory cell array. The control logic circuit is configured to control an operation of the memory cell array. The plurality of input/output pins receive a plurality of data signals from the controller. The DBI pin receives a DBI signal from the controller. The interface circuit count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the data signals and the DBI signal and provide the data signals to the page buffer or the control logic circuit based on the first number and the second number.
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公开(公告)号：US11736098B2
公开(公告)日：2023-08-22
申请号：US17866517
申请日：2022-07-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung Kim , Youngmin Jo , Chiweon Yoon , Byungkwan Chun , Byunghoon Jeong
CPC classification number: H03K5/14 , H03K5/135 , H03L7/0816 , H03K2005/00247
Abstract: A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.
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公开(公告)号：US11714579B2
公开(公告)日：2023-08-01
申请号：US17828176
申请日：2022-05-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seonkyoo Lee , Jeongdon Ihm , Chiweon Yoon , Byunghoon Jeong
CPC classification number: G06F3/0659 , G06F1/06 , G06F3/0613 , G06F3/0679 , G06F13/1668 , G11C16/0483 , G11C16/10 , G11C16/26
Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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公开(公告)号：US20230091026A1
公开(公告)日：2023-03-23
申请号：US17994296
申请日：2022-11-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Anil Kavala , Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.
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公开(公告)号：US10998888B2
公开(公告)日：2021-05-04
申请号：US16861903
申请日：2020-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongho Shin , Kyungtae Kang , Junha Lee , Tongsung Kim , Jangwoo Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A parameter monitoring circuit includes a code generation circuit configured to generate a first code, to which a first offset is applied, and a second code, to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by respectively applying the first code and the second code to a current parameter; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error in the current parameter, based on the first comparison result and the second comparison result.
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