公开(公告)号：US12211572B2

公开(公告)日：2025-01-28

申请号：US17680425

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungho Kim ,  Chulwoo Kim ,  Hyunsu Park ,  Jincheol Sim

IPC: G11C29/12 ,  G11C29/56

Abstract: A semiconductor device includes a multilevel receiver including a signal determiner receiving a plurality of multilevel signals and outputting a result of mutual comparison of the plurality of multilevel signals as an N-bit signal, where N is a natural number equal to or greater than 2. A decoder restores a valid signal among the N-bit signals from the signal determiner to an M-bit data signal, where M is a natural number less than N. A clock generator receives a reference clock signal, generates an input clock signal using the reference clock signal, inputs the input clock signal to the signal determiner, and determines a phase of the input clock signal based on an occurrence probability of an invalid signal not restored to the M-bit data signal among the N-bit signals.

公开(公告)号：US11501069B2

公开(公告)日：2022-11-15

申请号：US17048321

申请日：2019-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulwoo Kim

IPC: G06F3/04886 ,  G06F40/274

Abstract: Various embodiments of the present invention relate to an electronic device for inputting characters and a method of operation of same. At this time, the electronic device comprises a display, at least one processor, and a memory operatively connected to the processor, wherein the memory may store instructions that, when executed, cause the at least one processor to: detect at least one input word; determine a priority of a plurality of categories for a content on the basis of the at least one input word; determine at least one recommendation category on the basis of the determined priority of the plurality of categories; and control the display so as to display at least one content corresponding to the at least one determined recommendation category as at least one recommendation content for the at least one input word. Other embodiments may also be possible.

公开(公告)号：US11217539B2

公开(公告)日：2022-01-04

申请号：US16750370

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulwoo Kim

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Disclosed are package substrates and semiconductor packages including the same. A package substrate may have a plurality of corner regions; a core layer having a first surface and a second surface; an upper layer, which includes a plurality of first wiring structures and a plurality of first dielectric layers; and a lower layer, which includes a plurality of second wiring structures and a plurality of second dielectric layers. Additionally, an area proportion of top surfaces of the first wiring structures in the upper layer relative to a top surface of the upper layer on each of the corner regions is less than an area proportion of top surfaces of the second wiring structures in the lower layer relative to a top surface of the lower layer on each of the corner regions.

公开(公告)号：US11145637B2

公开(公告)日：2021-10-12

申请号：US16583051

申请日：2019-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Chulwoo Kim ,  Hyo-Chang Ryu ,  Yun Seok Choi

IPC: H01L25/16 ,  H01L23/528 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L21/78 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

公开(公告)号：US09620494B2

公开(公告)日：2017-04-11

申请号：US15260723

申请日：2016-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewoo Son ,  Chulwoo Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L21/768 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76879 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K3/4614 ,  H05K3/4626 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.

公开(公告)号：US11936409B2

公开(公告)日：2024-03-19

申请号：US17683476

申请日：2022-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulwoo Kim ,  Jonghyuck Choi ,  Seungwoo Park ,  Hyun Woo Cho ,  Tae-Jin Kim ,  Jae Suk Yu ,  Kil Hoon Lee ,  Young Hwan Chang

IPC: H04B1/04 ,  H04L25/03

CPC classification number: H04B1/04 ,  H04L25/03057

Abstract: A transmitter and a receiver are provided. The transmitter includes a processing unit configured to receive a clock signal and a data signal, set a value of a consecutive identical digit (CID) value related to the data signal and generate a modulation signal during a unit interval (UI) based on the data signal and the CID value, and a transmitter driver configured to output output signals having different voltage levels during the unit interval by receiving the modulation signal.

公开(公告)号：US11855041B2

公开(公告)日：2023-12-26

申请号：US17536547

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulwoo Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3511

Abstract: A semiconductor package includes a package substrate, an interposer on the package substrate, semiconductor devices in individual mounting regions on a first surface of the interposer, respectively, first conductive connection members, and a molding member on the interposer. The interposer has first bonding pads in the individual mounting regions, respectively. The semiconductor devices each have chip pads electrically connected to the first bonding pads. The first conductive connection members are between the first bonding pads and the chip pads. The molding member covers the semiconductor devices and fills gaps between the first surface of the interposer and the semiconductor devices. At least one of the individual mounting regions includes a pad-free region with a cross shape and pad regions defined by the pad-free region, and the first bonding pads are in the pad regions.

公开(公告)号：US11721679B2

公开(公告)日：2023-08-08

申请号：US17396308

申请日：2021-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Chulwoo Kim ,  Hyo-Chang Ryu ,  Yun Seok Choi

IPC: H01L25/16 ,  H01L23/528 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L21/78 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L25/16 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/95001

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

公开(公告)号：US11670565B2

公开(公告)日：2023-06-06

申请号：US17307181

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Chang Ryu ,  Chulwoo Kim ,  Juhyun Lyu ,  Sanghyun Lee ,  Yun Seok Choi

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/3675 ,  H01L24/32 ,  H01L25/0655 ,  H01L23/367 ,  H01L25/50 ,  H01L2224/32237 ,  H01L2924/3511

Abstract: A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.

公开(公告)号：US11569145B2

公开(公告)日：2023-01-31

申请号：US17188332

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Lee ,  Juhyun Lyu ,  Unbyoung Kang ,  Chulwoo Kim ,  Jongho Lee

IPC: H01L23/36 ,  H01L23/40 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.