公开(公告)号：US11728297B2

公开(公告)日：2023-08-15

申请号：US17325384

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/05 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L23/3128 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/0362 ,  H01L2224/03416 ,  H01L2224/03418 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/03831 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05085 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/1312 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8181 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2224/05171 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2224/13111 ,  H01L2924/01079 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13113 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13118 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13116 ,  H01L2924/013 ,  H01L2924/00014

Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

公开(公告)号：US11018101B2

公开(公告)日：2021-05-25

申请号：US16398888

申请日：2019-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

公开(公告)号：US10325869B2

公开(公告)日：2019-06-18

申请号：US15870044

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer

公开(公告)号：US20180370210A1

公开(公告)日：2018-12-27

申请号：US15845458

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-yeong Kim ,  Pil-kyu Kang ,  Seok-ho Kim ,  Kwang-jin Moon ,  Na-ein Lee ,  Ho-jin Lee

IPC: B32B37/10 ,  H01L21/67 ,  H01L21/687 ,  H01L21/68 ,  H01L23/00

Abstract: Provided are a wafer bonding apparatus for accurately detecting a bonding state of wafers in a wafer bonding process and/or in a wafer bonding system including the wafer bonding apparatus. The wafer bonding apparatus includes a first supporting plate including a first surface and vacuum grooves for vacuum-absorption of a first wafer disposed on the first surface, a second supporting plate including a second surface facing the first surface. A second wafer is on the second surface. The wafer bonding apparatus and/or the wafer bonding system include a bonding initiator at a center portion of the first supporting plate, and an area sensor on the first supporting plate and configured to detect a propagation state of bonding between the first wafer and the second wafer.

公开(公告)号：US09935037B2

公开(公告)日：2018-04-03

申请号：US15408977

申请日：2017-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-kyu Kang ,  Ho-jin Lee ,  Byung-lyul Park ,  Tae-yeong Kim ,  Seok-ho Kim

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2225/06548

Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.