公开(公告)号：US12142652B2

公开(公告)日：2024-11-12

申请号：US17491965

申请日：2021-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Bae Kim ,  Kyungin Choi

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device is disclosed. The semiconductor device may include a semiconductor substrate including a protruding active pattern, a first gate pattern provided on the active pattern and extended to cross the active pattern, a first capping pattern provided on a top surface of the first gate pattern, the first capping pattern having a top surface, a side surface, and a rounded edge, and a first insulating pattern covering the side surface and the edge of the first capping pattern. A thickness of the first insulating pattern on the edge of the first capping pattern is different from a thickness of the first insulating pattern on outer side surfaces of the spacer patterns.

公开(公告)号：US20240072177A1

公开(公告)日：2024-02-29

申请号：US18345130

申请日：2023-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Kim ,  Yeondo Jung ,  Gwirim Park ,  Yelin Lee ,  Kichul Kim ,  Kyungin Choi

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/4908

Abstract: A semiconductor device includes channels spaced apart from each other on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a gate structure on the substrate and bordering lower and upper surfaces and a first sidewall of at least a portion of each of the channels, and a source/drain layer on a portion of the substrate adjacent to the gate structure and contacting second sidewalls of the channels. A nitrogen-containing portion is formed at an upper portion of an uppermost one of the channels, and may be doped with nitrogen.

公开(公告)号：US11791400B2

公开(公告)日：2023-10-17

申请号：US17643935

申请日：2021-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Seung Hun Lee ,  Dahye Kim ,  Ilgyou Shin ,  Sangmoon Lee ,  Kyungin Choi

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method includes forming an active pattern on a substrate, the active pattern comprising first semiconductor patterns and second semiconductor patterns, which are alternately stacked, forming a capping pattern on a top surface and a sidewall of the active pattern, performing a deposition process on the capping pattern to form an insulating layer, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer. The capping pattern has a crystalline structure and is in physical contact with sidewalls of the first semiconductor patterns and sidewalls of the second semiconductor patterns.

公开(公告)号：US20230223438A1

公开(公告)日：2023-07-13

申请号：US18182893

申请日：2023-03-13

Applicant: Samsung Electronics Co, Ltd.

Inventor： Haejun YU ,  Kyungin Choi ,  Seung Hun Lee

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L29/4991 ,  H01L29/42392 ,  H01L29/66553 ,  H01L27/092

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.

公开(公告)号：US11417731B2

公开(公告)日：2022-08-16

申请号：US17128153

申请日：2020-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US11380760B2

公开(公告)日：2022-07-05

申请号：US17028042

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin Choi ,  Hyunchul Song ,  Sunjung Kim ,  Taegon Kim ,  Seong Hoon Jeong

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L21/308 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

公开(公告)号：US20220068920A1

公开(公告)日：2022-03-03

申请号：US17524128

申请日：2021-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Dahye Kim ,  Jaemun Kim ,  Jinbum Kim ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/165 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762

Abstract: Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.

公开(公告)号：US10522537B2

公开(公告)日：2019-12-31

申请号：US15937093

申请日：2018-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhwa Kim ,  Kyungin Choi ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/08 ,  H01L27/088 ,  H01L21/768 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/02 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/311

Abstract: An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.

公开(公告)号：US10312153B2

公开(公告)日：2019-06-04

申请号：US15914125

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Ah-Young Cheon ,  Kwang-Yong Yang ,  Myungil Kang ,  Dohyoung Kim ,  YoonHae Kim

IPC: H01L29/66 ,  H01L21/265 ,  H01L27/092 ,  H01L29/165 ,  H01L21/8238

Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.

公开(公告)号：US09793381B2

公开(公告)日：2017-10-17

申请号：US15131611

申请日：2016-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Dongwoo Kim ,  Chang Woo Sohn ,  Youngmoon Choi

IPC: H01L29/66 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/3065

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure extending in a first direction on a substrate, forming a sacrificial gate pattern extending in a second direction to intersect the fin structure, forming a gate spacer layer covering the fin structure and the sacrificial gate pattern, providing a first ion beam having a first incident angle range and a second ion beam having a second incident angle range to the substrate, patterning the gate spacer layer using the first ion beam and the second ion beam to form gate spacers on sidewalls of the sacrificial gate pattern, forming source/drain regions at both sides of the sacrificial gate patterns, and replacing the sacrificial gate pattern with a gate electrode.