公开(公告)号：US09899272B2

公开(公告)日：2018-02-20

申请号：US15234170

申请日：2016-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poren Tang ,  Sunjung Steve Kim ,  Moon Seung Yang ,  Seung Hun Lee ,  Hyun Jung Lee ,  Geun Hee Jeong

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8258

CPC classification number: H01L21/823892 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/78

Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.

公开(公告)号：US09608114B2

公开(公告)日：2017-03-28

申请号：US14989956

申请日：2016-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Kim ,  Seung Hun Lee ,  Sunjung Kim ,  Hyun Jung Lee ,  Bonyoung Koo

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/7849 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/785

Abstract: A semiconductor device includes a buffer layer on a substrate, the buffer layer having a lattice constant different from that of the substrate, a fin structure upwardly protruding from the buffer layer, a gate electrode crossing over the fin structure, a cladding layer at a side of the fin structure and covering a top surface and sidewalls of the fin structure, and an interfacial layer between the cladding layer and the fin structure, the interfacial layer including a same element as the buffer layer.

公开(公告)号：US09508832B2

公开(公告)日：2016-11-29

申请号：US14749037

申请日：2015-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Jung Lee ,  Bonyoung Koo ,  Sunjung Kim ,  Jongryeol Yoo ,  Seung Hun Lee ,  Poren Tang

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/336 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/3085 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807

Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.

Abstract translation: 制造半导体器件的方法包括在衬底上形成沟道层，在沟道层上形成牺牲层，在牺牲层上形成硬掩模图案，并使用硬掩模图案作为蚀刻掩模进行图案化处理，形成 通道部分具有​​暴露的顶表面。 通道和牺牲层可由硅锗形成，并且牺牲层的锗含量可高于沟道层的锗含量。

公开(公告)号：US09437681B2

公开(公告)日：2016-09-06

申请号：US14709696

申请日：2015-05-12

Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

Inventor： Seung Hun Lee ,  Geert Eneman

IPC: H01L21/70 ,  H01L29/10 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41783 ,  H01L29/7848 ,  H01L29/7849

Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.

Abstract translation: 公开了CMOS半导体FinFET器件和用于制造CMOS半导体FinFET器件的方法。 器件可以包括在包含SiGe的公共应变松弛缓冲层上具有包含Ge的沟道区的nFinFET和pFinFET。 通道区中Ge的浓度高于应变松弛缓冲层中Ge的浓度。 器件还包括用于nFinFET的源极/漏极区域，源极/漏极区域包括SiGe; 以及用于pFinFET的源极/漏极区域，第二源极/漏极区域包括Ge。

公开(公告)号：US12100735B2

公开(公告)日：2024-09-24

申请号：US18115913

申请日：2023-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu Edward Cho ,  Seung Soo Hong ,  Geum Jung Seong ,  Seung Hun Lee ,  Jeong Yun Lee

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0869 ,  H01L29/165 ,  H01L29/7848 ,  H10B10/12

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

公开(公告)号：US20230275092A1

公开(公告)日：2023-08-31

申请号：US18143767

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Jinbum Kim ,  Haejun Yu ,  Seung Hun Lee

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.

公开(公告)号：US11735663B2

公开(公告)日：2023-08-22

申请号：US17565650

申请日：2021-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum Kim ,  Gyeom Kim ,  Da Hye Kim ,  Jae Mun Kim ,  Il Gyou Shin ,  Seung Hun Lee ,  Kyung In Choi

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.

公开(公告)号：US11688778B2

公开(公告)日：2023-06-27

申请号：US17141513

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong Ha ,  Dongwoo Kim ,  Gyeom Kim ,  Yong Seung Kim ,  Pankwi Park ,  Seung Hun Lee

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US11594598B2

公开(公告)日：2023-02-28

申请号：US17546326

申请日：2021-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk Jang ,  Seung Hun Lee ,  Su Jin Jung ,  Young Dae Cho

IPC: H01L29/08 ,  H01L29/786 ,  H01L29/167 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.

公开(公告)号：US20230059169A1

公开(公告)日：2023-02-23

申请号：US17718795

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Dongmyoung Kim ,  Cheol Kim ,  Dongsuk Shin ,  Woogwan Shim ,  Seung Hun Lee ,  Soonwook Jung

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device includes: an active pattern disposed on a substrate; a source/drain pattern disposed on the active pattern; a channel pattern connected to the source/drain pattern, wherein the channel pattern includes semiconductor patterns stacked on each other and spaced apart from each other; and a gate electrode disposed on the channel pattern and extending in a first direction, wherein the gate electrode includes: a channel neighboring part adjacent to a first sidewall of a first semiconductor pattern of the stacked semiconductor patterns; and a body part spaced apart from the first semiconductor pattern, wherein the channel neighboring part is disposed between the body part and the first semiconductor pattern, wherein the first sidewall of the first semiconductor pattern has a first width, wherein the channel neighboring part has a second width less than the first width. The body part has a third width greater than the second width.