公开(公告)号：US20190080754A1

公开(公告)日：2019-03-14

申请号：US16119416

申请日：2018-08-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Numerous embodiments of methods for writing to a resistive random access memory (RRAM) cell are disclosed. In one embodiment, the system verifies if a current through the RRAM cell exceeds a threshold value, and if it does not, the system executes a concurrent write-while-verify operation. In another embodiment, the system verifies if current through the RRAM cell has reached a target value, and if it has not, the system executes a write operation and then verifies the write operation using a current comparison.

公开(公告)号：US09721958B2

公开(公告)日：2017-08-01

申请号：US15003659

申请日：2016-01-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Chun-Ming Chen ,  Man-Tang Wu ,  Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L21/336 ,  H01L27/11524 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11536 ,  H01L21/306

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

公开(公告)号：US20170125603A1

公开(公告)日：2017-05-04

申请号：US15294174

申请日：2016-10-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Jeng-Wei Yang ,  Nhan Do

IPC: H01L29/788 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7883 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66825

Abstract: A non-volatile memory cell that includes a silicon substrate, source and drain regions formed in the silicon substrate (where a channel region of the substrate is defined between the source and drain regions), a metal floating gate disposed over and insulated from a first portion of the channel region, a metal control gate disposed over and insulated from the metal floating gate, a polysilicon erase gate disposed over and insulated from the source region, and a polysilicon word line gate disposed over and insulated from a second portion of the channel region.

公开(公告)号：US09570581B2

公开(公告)日：2017-02-14

申请号：US15091202

申请日：2016-04-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Willem-Jan Toren ,  Xian Liu ,  Gerhard Metzger-Brueckl ,  Nhan Do ,  Stephan Wege ,  Nadia Miridi ,  Chieng-Sheng Su ,  Cecile Bernardi ,  Liz Cuevas ,  Florence Guyot ,  Yueh-Hsin Chen ,  Henry Om'mani ,  Mandana Tadayoni

IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L27/115 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11568

Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

Abstract translation: 用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有源区，每个有源区具有沿第一方向的轴。 在垂直于第一方向的第二方向上，第一绝缘材料位于每个堆叠栅极结构之间。 每个堆叠栅极结构在有源区域上具有第二绝缘材料，在第二绝缘材料上方的电荷保持栅极，电荷保持栅极上方的第三绝缘材料以及位于第三绝缘材料上的控制栅极的第一部分。 控制栅极的第二部分在控制栅极的第一部分之上，并且与第一部分相邻并且在第二方向上延伸。 第四绝缘材料位于控制栅极的第二部分之上。

公开(公告)号：US09431126B2

公开(公告)日：2016-08-30

申请号：US14214097

申请日：2014-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/3486 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

Abstract translation: 一种用于使用编程电压的重复脉冲编程单元的非易失性存储器件和方法，具有交错读取操作以确定读取电流的电平，直到达到期望的编程状态。 每个连续的编程脉冲具有相对于先前脉冲增加阶跃值的一个或多个编程电压。 对于单级单元类型，在达到第一读取电流阈值之后，每个单元从编程脉冲中单独地移除，并且此后的一个或多个猝发脉冲的步长值增加。 对于多级单元类型，步长值在其中一个单元达到第一读取电流阈值后下降，一些单元在达到第二读取电流阈值之后单独地从编程脉冲中移除，而其他单元在编程脉冲之后被单独从编程脉冲中移除 达到第三个读取电流阈值。

公开(公告)号：US20160181517A1

公开(公告)日：2016-06-23

申请号：US14582089

申请日：2014-12-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Nhan Do ,  Hieu Van Tran ,  Hung Quoc Nguyen

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/16 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/50 ,  G11C2213/52 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1273 ,  H01L45/146

Abstract: A memory device (and method of making and using the memory device) includes a first electrode of conductive material, a second electrode of conductive material, and a layer transition metal oxide material that includes first and second elongated portions meeting each other at a sharp corner. Each of the first and second elongated portions is disposed between and in electrical contact with the first and second electrodes.

Abstract translation: 存储器件（以及制造和使用存储器件的方法）包括导电材料的第一电极，导电材料的第二电极和层过渡金属氧化物材料，其包括在锐角处相互相遇的第一和第二细长部分 。 第一和第二细长部分中的每一个设置在第一和第二电极之间并与之电接触。

公开(公告)号：US20140307511A1

公开(公告)日：2014-10-16

申请号：US14252929

申请日：2014-04-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Jinho Kim ,  Xian Liu

IPC: H01L27/115 ,  G11C16/12 ,  G11C16/14 ,  H01L29/66

CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region.

Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，用于控制其导电性。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘，以控制其导电性。 擦除栅极至少部分地布置在浮栅上并与浮栅绝缘。 导电耦合栅极设置在沟槽中，与浮动栅极相邻并与其隔离，并且与源极区域隔离并且绝缘。

公开(公告)号：US20240257880A1

公开(公告)日：2024-08-01

申请号：US18104228

申请日：2023-01-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Louisa Schneider ,  Xian Liu ,  Steven Lemke ,  Parviz Ghazavi ,  Jinho Kim ,  Henry A. Om'Mani ,  Hieu Van Tran ,  Nhan Do

IPC: G11C16/16 ,  H01L23/48 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/16 ,  H01L23/481 ,  H01L29/42328 ,  H10B41/10 ,  H10B41/27

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

公开(公告)号：US11594453B2

公开(公告)日：2023-02-28

申请号：US17716950

申请日：2022-04-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L21/77 ,  H01L27/11517 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

公开(公告)号：US11538532B2

公开(公告)日：2022-12-27

申请号：US17199383

申请日：2021-03-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  Chunming Wang ,  Nhan Do ,  Hieu Van Tran

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F11/14 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H03K19/20

Abstract: Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.